Patents by Inventor Fu-Lung Hsueh

Fu-Lung Hsueh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR DEVICE DESIGN SYSTEM AND METHOD OF USING THE SAME
    Publication number: 20130311957
    Abstract: A circuit design system includes a schematic design tool configured to generate schematic information and pre-coloring information for a circuit. The circuit design system also includes a netlist file configured to store the schematic information and the pre-coloring information on a non-transitory computer readable medium and an extraction tool configured to extract the pre-coloring information from the netlist file. A layout design tool, included in the circuit design system, is configured to design at least one mask based on the schematic information and the pre-coloring information. The circuit design system further includes a layout versus schematic comparison tool configured to compare the at least one mask to the schematic information and the pre-coloring information.
    Type: Application
    Filed: May 18, 2012
    Publication date: November 21, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Hsien CHANG, Yung-Chow PENG, Fu-Lung HSUEH
  • Clock and data recovery using LC voltage controlled oscillator and delay locked loop
    Patent number: 8588358
    Abstract: A clock and data recovery (CDR) circuit includes an inductor-capacitor voltage controlled oscillator (LCVCO) configured to generate a clock signal with a clock frequency. A delay locked loop (DLL) is configured to receive the clock signal from the LCVCO and generate multiple clock phases. A charge pump is configured to control the LCVCO. A phase detector is configured to receive a data input and the multiple clock phases from the DLL, and to control the first charge pump in order to align a data edge of the data input and the multiple clock phases.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: November 19, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan-Hong Chern, Chih-Chang Lin, Ming-Chieh Huang, Fu-Lung Hsueh
  • Circuit for reducing negative bias temperature instability
    Patent number: 8570068
    Abstract: A circuit includes an operational PMOS transistor of a logic gate driver. A control circuit is configured to turn off the operational PMOS transistor during a standby mode. The circuit also includes a sacrificial PMOS transistor coupled to an output node. The operational PMOS transistor is coupled to the output node. The sacrificial PMOS transistor is configured to keep the output node at a logical 1 during the standby mode.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: October 29, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan-Hong Chern, Fu-Lung Hsueh, Ming-Chieh Huang, Bryan Sheffield, Chih-Chang Lin
  • Motion detection using capacitor having different work function materials
    Patent number: 8549922
    Abstract: An apparatus for detecting mechanical displacement in a micro-electromechanical system includes a capacitor having first and second plates spaced from one another, the first and second plates having different work functions and being electrically connected with each other. The capacitor plates are movable with respect to one another such that a spacing between the plates changes in response to a force. A current through the capacitor represents a rate of change in the spacing between the plates at a given time.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: October 8, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Alexander Kalnitsky, Fu-Lung Hsueh
  • RF CALIBRATION THROUGH-CHIP INDUCTIVE COUPLING
    Publication number: 20130241634
    Abstract: An integrated circuit includes a first chip and a second chip coupled to the first chip in a vertical stack. The first chip includes a radio frequency circuit and a first coil electrically coupled to the radio frequency circuit. The second chip includes a calibration circuit and a second coil electrically coupled to the calibration circuit. The calibration circuit is configured to calibrate the radio frequency circuit disposed on the first chip through inductive coupling between the first and second coils.
    Type: Application
    Filed: March 14, 2012
    Publication date: September 19, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsieh-Hung HSIEH, Yi-Hsuan LIU, Tzu-Jin YEH, Chewn-Pu JOU, Fu-Lung HSUEH
  • Method and apparatus for low power semiconductor chip layout and low power semiconductor chip
    Patent number: 8539388
    Abstract: A layout system is described comprising a layout unit configured to layout cells in a mask design for a semiconductor chip based on library cells for a specified process node; a non-critical path determination unit configured to determine a non-critical path in the semiconductor chip; a cell determination unit configured to determine a group of cells in the mask design that form a part of the non-critical path and determine the corresponding library cell for at least one of the group of cells; a library cell modifying unit configured to modify one or more corresponding library cells to form a corresponding modified library cell; and a cell replacement unit configured to replace a library cell in the group of cells in the mask design that form a part of the non-critical path with the corresponding modified library cell.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: September 17, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chewn-Pu Jou, Ming-Tsun Lin, Fu-Lung Hsueh, Shauh-Teh Juang
  • Low minimum power supply voltage level shifter
    Patent number: 8493124
    Abstract: A level shifter includes one PMOS and two NMOS transistors. A source of the first NMOS transistor is coupled to a low power supply voltage. An input signal is coupled to a gate of the first NMOS transistor and a source of the second NMOS transistor. The input signal has a voltage level up to a first power supply voltage. A source of the PMOS transistor is coupled to a second power supply voltage, higher than the first power supply voltage. An output signal is coupled between the PMOS and the first NMOS transistors. The first NMOS transistor is arranged to pull down the output signal when the input signal is a logical 1, and the second NMOS transistor is arranged to enable the PMOS transistor to pull up the output signal to a logical 1 at the second power supply voltage when the input signal is a logical 0.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: July 23, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan-Hong Chern, Fu-Lung Hsueh, Ming-Chieh Huang, Chih-Chang Lin
  • Method and apparatus for amplifying a time difference
    Patent number: 8476972
    Abstract: A time amplifier circuit has first and second inverters and first and second pull-down paths. Each inverter includes a first NMOS transistor and a first PMOS transistor. A source of the first NMOS transistor is coupled to a ground node directly or through a first additional NMOS transistor having a gate coupled to a respective input node. The first and second inverters are coupled to first and second input nodes and to first and second output nodes, respectively. The first pull-down path is from the first output node to the ground node and is enabled in response to the first input signal and the second output signal being high. The second pull-down path is from the second output node to ground and is enabled in response to the second input signal and the first output signal being high.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: July 2, 2013
    Assignees: Taiwan Semiconductor Manufacturing Co., Ltd, National Taiwan University
    Inventors: You-Jen Wang, Shen-Iuan Liu, Feng Wei Kuo, Chewn-Pu Jou, Fu-Lung Hsueh
  • Millimeter-wave wideband frequency doubler
    Patent number: 8451033
    Abstract: A millimeter-wave wideband frequency doubler stage for use in a distributed frequency doubler includes: a differential input pair of transistors, each transistor having respective gate, drain and source terminals, wherein the source terminals are coupled together to a first power supply node and the drain terminals are coupled together at a first node to a second power supply node; first and second pairs of bandpass gate lines coupled to the gate terminals of the transistors; and a pair of bandpass drain lines coupled to the drain terminals of the transistors.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: May 28, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yi Wu, Hsieh-Hung Hsieh, Ho-Hsiang Chen, Tzu-Jin Yeh, Chewn-Pu Jou, Fu-Lung Hsueh
  • CMOS image sensors formed of logic bipolar transistors
    Patent number: 8450672
    Abstract: An integrated circuit structure includes an image sensor cell, which further includes a photo transistor configured to sense light and to generate a current from the light.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: May 28, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shine Chung, Tao-Wen Chung, Fu-Lung Hsueh
  • INTEGRATED CIRCUITS WITH ELECTRICAL FUSES AND METHODS OF FORMING THE SAME
    Publication number: 20130126979
    Abstract: A method of forming an integrated circuit includes forming at least one transistor over a substrate. Forming the at least one transistor includes forming a gate dielectric structure over a substrate. A work-function metallic layer is formed over the gate dielectric structure. A conductive layer is formed over the work-function metallic layer. A source/drain (S/D) region is formed adjacent to each sidewall of the gate dielectric structure. At least one electrical fuse is formed over the substrate. Forming the at least one electrical fuse includes forming a first semiconductor layer over the substrate. A first silicide layer is formed on the first semiconductor layer.
    Type: Application
    Filed: November 22, 2011
    Publication date: May 23, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong CHERN, Fu-Lung HSUEH, Kuoyuan (Peter) HSU
  • Level shifters having diode-connected devices for input-output interfaces
    Patent number: 8436671
    Abstract: A level shifter includes an input node, an output node, a pull-up transistor, a pull-down transistor, and at least one diode-connected device coupled between the pull-up transistor and the pull-down transistor. The level shifter is arranged to be coupled to a high power supply voltage, to receive an input signal having a first voltage level at the input node, and to supply an output signal having a second voltage level at the output node. The high power supply voltage is higher than the first voltage level. The at least one diode-connected device allows the output signal to be pulled up to about a first diode voltage drop below the high power supply voltage and/or to be pulled down to about a second diode voltage drop above ground. The first diode voltage drop and the second diode voltage drop are from the at least one diode-connected device.
    Type: Grant
    Filed: August 19, 2010
    Date of Patent: May 7, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan-Hong Chern, Fu-Lung Hsueh, Chih-Chang Lin, Yuwen Swei, Ming-Chieh Huang
  • Current-controlled oscillator (CCO) based PLL
    Patent number: 8432204
    Abstract: A PLL circuit includes a phase frequency detector; a programmable charge pump coupled to an output of the phase frequency detector; a loop filter coupled to an output of the charge pump, the loop filter providing a fine tuning voltage; a first voltage-to-current converter, the first voltage-to-current converter providing a fine tuning current corresponding to the fine tuning voltage; a current-controlled oscillator (CCO); a feedback divider coupled to an output of the CCO and an input of the phase frequency detector; and an analog calibration circuit. The analog calibration circuit provides a coarse adjustment current for coarse adjustments to a frequency pivot point for an oscillator frequency of the CCO, wherein the CCO generates a frequency signal at an output responsive to a summed coarse adjustment and fine tuning current, wherein the frequency pivot point is continuously adjustable.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: April 30, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chan-Hong Chern, Ming-Chieh Huang, Tao Wen Chung, Chih-Chang Lin, Yuwen Swei, Fu-Lung Hsueh
  • Low-noise amplifier with gain enhancement
    Patent number: 8427240
    Abstract: A low-noise amplifier (“LNA”) includes a first cascode gain stage including a first complementary metal oxide semiconductor (“CMOS”) transistor configured to receive a radio frequency (“RF”) input signal and a second CMOS transistor coupled to an output node. The first inductive gate network is coupled to a gate of the second CMOS transistor for increasing a gain of the first cascode gain stage. The first inductive gate network has a non-zero inductive input impedance and includes at least one passive circuit element.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: April 23, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsieh-Hung Hsieh, Po-Yi Wu, Ho-Hsiang Chen, Chewn-Pu Jou, Fu-Lung Hsueh
  • Advisory system for verifying sensitive circuits in chip-design
    Patent number: 8418098
    Abstract: A verification system for verifying an integrated circuit design is provided. The verification system includes a functional block finding module configured to identify potential sensitive circuits in the integrated circuit design; and a search module. The search module is configured to find sensitive circuits from the potential sensitive circuits; and verify the sensitive circuits.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: April 9, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Heng Huang, Gary Lin, Chu-Fu Chen, Yi-Kan Cheng, Fu-Lung Hsueh
  • PHASE LOCKED LOOP CALIBRATION
    Publication number: 20130082754
    Abstract: An inductor-capacitor phase locked loop (LCPLL) includes an inductor-capacitor voltage controlled oscillator (LCVCO) that provides an output frequency. A calibration circuit includes two comparators and provides a coarse tune signal to the LCVCO. The two comparators respectively compare the loop filter signal with a first reference voltage and a second reference voltage that is higher than the first reference voltage to supply a first and second comparator output, respectively. The calibration circuit is capable of adjusting the coarse tune signal continuously in voltage values and adjusts the coarse tune signal based on the two comparator outputs. A loop filter provides a loop filter signal to the calibration circuit and a fine tune signal to the LCVCO. A coarse tune frequency range is greater than a fine tune frequency range.
    Type: Application
    Filed: October 4, 2011
    Publication date: April 4, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong CHERN, Ming-Chieh HUANG, Tao Wen CHUNG, Chih-Chang LIN, Fu-Lung HSUEH, Yuwen SWEI
  • CONTACTLESS COMMUNICATIONS USING FERROMAGNETIC MATERIAL
    Publication number: 20130038418
    Abstract: A communications structure comprises a first semiconductor substrate having a first coil, and a second semiconductor substrate having a second coil above the first semiconductor substrate. Inner edges of the first and second coils define a boundary of a volume that extends below the first coil and above the second coil. A ferromagnetic core is positioned at least partially within the boundary, such that a mutual inductance is provided between the first and second coils for wireless transmission of signals or power between the first and second coils.
    Type: Application
    Filed: August 10, 2011
    Publication date: February 14, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ping-Lin Yang, Jun-De Jin, Fu-Lung Hsueh, Sa-Lly Liu, Tong-Chern Ong, Chun-Jung Lin, Ya-Chen Kao
  • Junction varactor for ESD protection of RF circuits
    Patent number: 8334571
    Abstract: An ESD protection device includes a first well of a first semiconductor type disposed in a substrate of a second semiconductor type forming a first diode. A second well of the second semiconductor type is formed in the substrate to form a second diode with the first well. A first plurality of doped regions of the first semiconductor type are formed in an upper surface of the first well. A second plurality of doped regions of the second semiconductor type are formed in the upper surface of the first well forming a third diode with the first well. A plurality of STI regions are formed in the upper surface of the first well. Each STI region is disposed between a doped region of the first and second semiconductor types. The third diode provides a current bypass when an ESD voltage spike is received at one of the first or second plurality of doped regions.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: December 18, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Hsien Tsai, Tzu-Jin Yeh, Chewn-Pu Jou, Fu-Lung Hsueh
  • Circuit and method for radio frequency amplifier
    Patent number: 8324970
    Abstract: A radio frequency amplifier circuit includes a substrate that is capable of receiving a substrate bias voltage. The source of a transistor is capable of receiving a source bias voltage. The drain of the transistor is capable of receiving a drain bias voltage. The gate of the transistor is located between the source and the drain. A radio frequency input signal is coupled to the gate. A substrate bias circuit provides the substrate bias voltage. The substrate bias voltage and the source bias voltage forward bias the first diode formed by the source and the substrate. The substrate bias voltage and the drain bias voltage reverse bias the second diode formed by the drain and the substrate.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: December 4, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chewn-Pu Jou, Fu-Lung Hsueh, Sally Liu
  • ESD protection circuit for RFID tag
    Patent number: 8324658
    Abstract: An electrostatic discharge (ESD) protection circuit structure includes a dual directional silicon controlled rectifier (SCR) formed in a substrate. The SCR includes first and second P-wells laterally interposed by an N-well. A deep N-well is disposed underneath the P-wells and the N-well. First and second N-type regions are disposed in the first and second P-wells, respectively, and are coupled to a pair of pads. First and second P-type regions are disposed in the first and second P-wells, respectively, are coupled to the pads, and are disposed closer to the N-well than the first and second N-type regions, respectively.
    Type: Grant
    Filed: April 14, 2010
    Date of Patent: December 4, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Hsien Tsai, Chewn-Pu Jou, Fu-Lung Hsueh, Ming-Hsiang Song