Patents by Inventor Fu-Lung Hsueh

Fu-Lung Hsueh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dual-Side Illumination Image Sensor Chips and Methods for Forming the Same
    Publication number: 20140138520
    Abstract: A Dual-Side Illumination (DSI) image sensor chip includes a first image sensor chip configured to sense light from a first direction, and a second image sensor chip aligned to, and bonded to, the first image sensor chip. The second image sensor chip is configured to sense light from a second direction opposite the first direction.
    Type: Application
    Filed: November 21, 2012
    Publication date: May 22, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Min Liu, Honyih Tu, Calvin Yi-Ping Chao, Fu-Lung Hsueh
  • Built-in self-test circuit for voltage controlled oscillators
    Patent number: 8729968
    Abstract: A built-in self-test circuit for testing a voltage controlled oscillator comprises a voltage controlled oscillator, a buffer having an input coupled to an output of the voltage controlled oscillator and a radio frequency peak detector coupled to the output of the buffer. The radio frequency peak detector is configured to receive an ac signal from the voltage controlled oscillator and generate a dc value proportional to the ac signal at an output of the radio frequency peak detector. Furthermore, the output of the radio frequency peak detector generates a dc value proportional to an amplitude of the ac signal from the voltage controlled oscillator when the voltage controlled oscillator functions correctly. On the other hand, the output of the radio frequency peak detector is at zero volts when the voltage controlled oscillator fails to generate an ac signal.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: May 20, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsieh-Hung Hsieh, Ming Hsien Tsai, Tzu-Jin Yeh, Chewn-Pu Jou, Fu-Lung Hsueh
  • Automatic misalignment balancing scheme for multi-patterning technology
    Patent number: 8709684
    Abstract: Some aspects of the present disclosure provide for a method of automatically balancing mask misalignment for multiple patterning layers to minimize the consequences of mask misalignment. In some embodiments, the method defines a routing grid for one or more double patterning layers within an IC layout. The routing grid has a plurality of vertical grid lines extending along a first direction and a plurality of horizontal grid lines extending along a second, orthogonal direction. Alternating lines of the routing grid in a given direction (e.g., the horizontal and vertical direction) are assigned different colors. Shapes on the double patterning layers are then routed along the routing grid in a manner that alternates between different colored grid lines. By routing in such a manner, variations in capacitive coupling caused by mask misalignment are reduced.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: April 29, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chan-Hong Chern, Tao Wen Chung, Ming-Chieh Huang, Chih-Chang Lin, Tsung-Ching (Jim) Huang, Fu-Lung Hsueh
  • INDUCTOR WITH CONDUCTIVE TRACE
    Publication number: 20140111273
    Abstract: Among other things, an inductor comprising a conductive trace and a method for forming the inductor are provided. The inductor comprises a magnetic structure, such as a ferrite core. A molding material, such as a dielectric, is formed around the magnetic structure. A conductive trace, comprising one or more conductive pillars interconnected by one or more upper interconnects and one or more lower interconnects, is formed around the magnetic structure to form the inductor. The conductive trace allows physical limitations associated with winding a wire to be avoided, and thus allows the inductor to be smaller than wire wound inductors. In one example, the inductor is formed within an integrated circuit package comprising an active device, such as an integrated circuit. In this way, the inductor can be connected to the integrated circuit within the integrated circuit package.
    Type: Application
    Filed: October 19, 2012
    Publication date: April 24, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chewn-Pu Jou, Chuei-Tang Wang, Fu-Lung Hsueh
  • Methods of fabricating bipolar junction transistors having a fin
    Patent number: 8703571
    Abstract: A method of forming a semiconductor device is provided. The method includes forming a first fin above a substrate, forming a first emitter region in a first portion of the first fin, forming a first collector region in a second portion of the first fin, and forming a first base region in a third portion of the first fin. The third portion of the first fin is disposed underneath a first gate electrode. The method further includes forming a second fin adjacent to the first fin and above the substrate. The second fin is composed of a semiconductor material. The method also includes forming a first base contact over the second fin. The first base contact is coupled to the first base region through the second fin, the substrate, and the first fin.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: April 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yao Ke, Tao-Wen Chung, Shine Chung, Fu-Lung Hsueh
  • INTEGRATED CIRCUIT LAYOUT
    Publication number: 20140109033
    Abstract: A layout of a portion of an integrated circuit includes first and second cell structures, each including a first or second dummy gate electrode disposed on a first or second boundary of the corresponding first or second cell structure, a first or second edge gate electrode disposed adjacent to the corresponding first or second dummy gate electrode, and a first or second oxide definition (OD) region having a first or second edge. The second boundary faces the first boundary without abutting the first boundary. The first edge of the first OD region is substantially aligned with the closest edge of the first dummy gate electrode or overlaps the first dummy gate electrode. A distance from the first edge gate electrode to the farthest edge of the first dummy gate electrode is greater than the distance from the first edge gate electrode to the first edge of the first OD region.
    Type: Application
    Filed: December 19, 2013
    Publication date: April 17, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong CHERN, Fu-Lung HSUEH, Li-Chun TIEN
  • Phase locked loop calibration
    Patent number: 8698566
    Abstract: An inductor-capacitor phase locked loop (LCPLL) includes an inductor-capacitor voltage controlled oscillator (LCVCO) that provides an output frequency. A calibration circuit includes two comparators and provides a coarse tune signal to the LCVCO. The two comparators respectively compare the loop filter signal with a first reference voltage and a second reference voltage that is higher than the first reference voltage to supply a first and second comparator output, respectively. The calibration circuit is capable of adjusting the coarse tune signal continuously in voltage values and adjusts the coarse tune signal based on the two comparator outputs. A loop filter provides a loop filter signal to the calibration circuit and a fine tune signal to the LCVCO. A coarse tune frequency range is greater than a fine tune frequency range.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: April 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan-Hong Chern, Ming-Chieh Huang, Tao Wen Chung, Chih-Chang Lin, Fu-Lung Hsueh, Yuwen Swei
  • 3D-STACKED BACKSIDE ILLUMINATED IMAGE SENSOR AND METHOD OF MAKING THE SAME
    Publication number: 20140077057
    Abstract: A stacked image sensor and method for making the same are provided. The stacked image sensor includes an upper chip with a pixel array thereon. The second chip includes a plurality of column circuits and row circuits associated with the columns and rows of the pixel array and disposed in respective column circuit and row circuit regions that are arranged in multiple groups. Inter-chip bonding pads are formed on each of the chips. The inter-chip bonding pads on the second chip are arranged linearly and are contained within the column circuit regions and row circuit regions in one embodiment. In other embodiments, the inter-chip bonding pads are staggered with respect to each other. In some embodiments, the rows and columns of the pixel array include multiple signal lines and the corresponding column circuit regions and row circuit regions also include multiple inter-chip bonding pads.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Calvin Yi-Ping CHAO, Kuo-Yu CHOU, Fu-Lung HSUEH
  • Method and Apparatus for RFID Tag Testing
    Publication number: 20140055155
    Abstract: A semiconductor wafer includes a plurality of dies and at least one test probe. Each of the plurality of dies includes a radio frequency identification (RFID) tag circuit. The at least one test probe includes a plurality of probe pads. The plurality of probe pads is configured to transmit power signals and data to each of the plurality of dies, and to receive test results from each of the plurality of dies. The data are transmitted to each of the plurality of dies in a serial manner. The test results of each of the plurality of dies are also transmitted to the plurality of probe pads in a serial manner.
    Type: Application
    Filed: October 18, 2012
    Publication date: February 27, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Hsiung Li, Kuang-Kai Yen, Yi-Hsuan Liu, Hsieh-Hung Hsieh, Chewn-Pu Jou, Fu-Lung Hsueh
  • Systems and methods of designing integrated circuits
    Patent number: 8661389
    Abstract: A method of designing an integrated circuit includes providing a cell library including a first and second cell structures. The cell structures each include a dummy gate electrode disposed on a boundary. An edge gate electrode is disposed adjacent to the dummy gate electrode. An oxide definition (OD) region has an edge disposed between the edge gate electrode and the dummy gate electrode. The method includes determining if the cell structures are to be abutted with each other. If so, the method includes abutting the cell structures. If not so, the method includes increasing areas of portions of the OD regions between the edge gate electrodes and the dummy gate electrodes.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: February 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan-Hong Chern, Fu-Lung Hsueh, Li-Chun Tien
  • DIVIDER-LESS PHASE LOCKED LOOP (PLL)
    Publication number: 20140049329
    Abstract: One or more techniques and systems for a divider-less phase locked loop (PLL) and associated phase detector (PD) are provided herein. In some embodiments, a pulse phase detector (pulsePD) signal, a voltage controlled oscillator positive differential (VCOP) signal, and a voltage controlled oscillator negative differential (VCON) signal are received. An up signal and a down signal for a first charge pump (CP) and an up signal and a down signal for a second CP are generated based on the pulsePD signal, the VCOP signal, and the VCON signal. For example, CP signals are generated to control the first CP and the second CP, respectively. In some embodiments, CP signals are generated such that the CPs facilitate adjustment of a zero crossing phase of the VCON and VCOP signals with respect to the pulsePD signal. In this manner, a divider-less PLL is provided, thus mitigating PLL power consumption.
    Type: Application
    Filed: August 15, 2012
    Publication date: February 20, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yen-Jen Chen, I-Ting Lee, Hsieh-Hung Hsieh, Chewn-Pu Jou, Fu-Lung Hsueh, Shen-Luan Liu
  • CLOCK AND DATA RECOVERY USING LC VOLTAGE CONTROLLED OSCILLATOR AND DELAY LOCKED LOOP
    Publication number: 20140044225
    Abstract: A clock and data recovery (CDR) circuit includes an inductor-capacitor voltage controlled oscillator (LCVCO) configured to generate a clock signal with a clock frequency. The CDR circuit further includes a delay locked loop (DLL) configured to receive the clock signal from the LCVCO and generate multiple clock phases and a first charge pump configured to control the LCVCO. The CDR circuit further includes a phase detector configured to receive a data input and the multiple clock phases from the DLL, and to align a data edge of the data input and the multiple clock phases.
    Type: Application
    Filed: October 21, 2013
    Publication date: February 13, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong CHERN, Chih-Chang LIN, Ming-Chieh HUANG, Fu-Lung HSUEH
  • LCD driver
    Patent number: 8648779
    Abstract: A method includes outputting a first signal from a first DAC decoder circuit in response to receiving a first number of bits of a digital control signal, outputting a second signal from a second DAC decoder circuit in response to receiving a second number of bits of the digital control signal, and alternately outputting one of the first and second signals to an LCD column from a buffer coupled to the first and second DAC decoder circuits. The first signal has a voltage level equal to one of a first plurality of voltage levels received at one of a first plurality of inputs of the first DAC decoder circuit. The second signal has a voltage level equal to one of a second plurality of voltage levels received at one of a second plurality of inputs of the second DAC decoder circuit.
    Type: Grant
    Filed: October 20, 2009
    Date of Patent: February 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fu-Lung Hsueh, Yung-Chow Peng, Kuo-Liang Deng
  • Automatic Misalignment Balancing Scheme for Multi-Patterning Technology
    Publication number: 20140038085
    Abstract: Some aspects of the present disclosure provide for a method of automatically balancing mask misalignment for multiple patterning layers to minimize the consequences of mask misalignment. In some embodiments, the method defines a routing grid for one or more double patterning layers within an IC layout. The routing grid has a plurality of vertical grid lines extending along a first direction and a plurality of horizontal grid lines extending along a second, orthogonal direction. Alternating lines of the routing grid in a given direction (e.g., the horizontal and vertical direction) are assigned different colors. Shapes on the double patterning layers are then routed along the routing grid in a manner that alternates between different colored grid lines. By routing in such a manner, variations in capacitive coupling caused by mask misalignment are reduced.
    Type: Application
    Filed: July 31, 2012
    Publication date: February 6, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chan-Hong Chern, Tao Wen Chung, Ming-Chieh Huang, Chih-Chang Lin, Tsung-Ching (Jim) Huang, Fu-Lung Hsueh
  • CIRCUIT FOR REDUCING NEGATIVE BIAS TEMPERATURE INSTABILITY
    Publication number: 20140028350
    Abstract: A control circuit comprises a first NOR gate, a first NMOS transistor, and a first PMOS transistor. The control circuit also comprises an output node. The control circuit further comprises a half latch keeper circuit coupled to a gate of the first NMOS transistor and to a gate of the first PMOS transistor. The half latch keeper circuit is configured to keep the output node at a logical 1 during a standby mode. The control circuit additionally comprises an operational PMOS transistor coupled to the output node. An output of the first NOR gate is coupled to a gate of the operational PMOS transistor. The control circuit is configured to turn off the operational PMOS transistor during the standby mode.
    Type: Application
    Filed: October 3, 2013
    Publication date: January 30, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong CHERN, Fu-Lung HSUEH, Ming-Chieh HUANG, Bryan SHEFFIELD, Chih-Chang LIN
  • Reconfigurable and Auto-Reconfigurable Resonant Clock
    Publication number: 20140028407
    Abstract: The present disclosure relates to a resonant clock system having a driver component, a clock load capacitor, and a reconfigurable inductor array. The driver component generates a driven input signal. The clock load capacitor is configured to receive the driven input signal. The inductor array is configured to have an effective inductance according to a selected frequency. The inductor array also generates a resonant signal at the selected frequency using the effective inductance.
    Type: Application
    Filed: July 26, 2012
    Publication date: January 30, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chan-Hong Chern, Tao Wen Chung, Chih-Chang Lin, Ming-Chieh Huang, Tsung-Ching Huang, Fu-Lung Hsueh
  • MOTION DETECTION USING CAPACITOR HAVING DIFFERENT WORK FUNCTION MATERIALS
    Publication number: 20140009175
    Abstract: An apparatus for detecting mechanical displacement in a micro-electromechanical system includes a capacitor having first and second plates spaced from one another, the first and second plates having different work functions and being electrically connected with each other. The capacitor plates are movable with respect to one another such that a spacing between the plates changes in response to a force. A current through the capacitor represents a rate of change in the spacing between the plates at a given time.
    Type: Application
    Filed: September 9, 2013
    Publication date: January 9, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Alexander KALNITSKY, Fu-Lung HSUEH
  • Method for substrate noise analysis
    Patent number: 8627253
    Abstract: In accordance with an embodiment, a method for substrate noise analysis comprises using a first processor based system, creating and simulating a circuit schematic comprising a multi-terminal model of a transistor, and thereafter, creating a layout based on properties represented in the circuit schematic and simulation results of the simulating. The multi-terminal model comprises a source terminal, a gate terminal, a drain terminal, a body terminal, and a guard-ring terminal.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: January 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Jin Yeh, Kal-Wen Tan, Chewn-Pu Jou, Sally Liu, Fu-Lung Hsueh
  • Multi-level electrical fuse using one programming device
    Patent number: 8619488
    Abstract: A method for programming a multi-level electrical fuse system comprises providing a fuse box with an electrical fuse and providing one of at least two fuse writing voltages to the electrical fuse to program the electrical fuse to one of at least two resistance states. The fuse box comprises at least one electrical fuse, a programming device serially coupled to the electrical fuse, and a variable power supply coupled to the fuse box and configured to generate two or more voltage levels.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: December 31, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Lung Lin, Jui-Jen Wu, Shine Chung, Fu-Lung Hsueh
  • CAPACTIVE LOAD PLL WITH CALIBRATION LOOP
    Publication number: 20130342247
    Abstract: A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage.
    Type: Application
    Filed: June 22, 2012
    Publication date: December 26, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chan-Hong CHERN, Tao Wen CHUNG, Ming-Chieh HUANG, Chih-Chang LIN, Tsung-Ching HUANG, Fu-Lung HSUEH