Patents by Inventor Fu-Lung Hsueh

Fu-Lung Hsueh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INTEGRATED CIRCUITS WITH RESISTORS
    Publication number: 20140367793
    Abstract: An integrated circuit includes a transistor. The transistor includes a first gate dielectric structure over a substrate, a work-function layer over the first gate dielectric structure, a conductive layer over the work-function layer, and a source/drain (S/D) region adjacent to each sidewall of the first gate dielectric structure. Additionally, the integrated circuit includes a resistor structure. The resistor structure further includes a first doped semiconductor layer over the substrate, wherein a top surface of the resistor structure is substantially planar with a top surface of the transistor.
    Type: Application
    Filed: September 2, 2014
    Publication date: December 18, 2014
    Inventors: Chan-Hong CHERN, Fu-Lung HSUEH
  • CAPACITIVE LOAD PLL WITH CALIBRATION LOOP
    Publication number: 20140347110
    Abstract: A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage.
    Type: Application
    Filed: August 11, 2014
    Publication date: November 27, 2014
    Inventors: Chan-Hong CHERN, Tao Wen CHUNG, Ming-Chieh HUANG, Chih-Chang LIN, Tsung-Ching HUANG, Fu-Lung HSUEH
  • Divider-less phase locked loop (PLL)
    Patent number: 8890626
    Abstract: One or more techniques and systems for a divider-less phase locked loop (PLL) and associated phase detector (PD) are provided herein. In some embodiments, a pulse phase detector (pulsePD) signal, a voltage controlled oscillator positive differential (VCOP) signal, and a voltage controlled oscillator negative differential (VCON) signal are received. An up signal and a down signal for a first charge pump (CP) and an up signal and a down signal for a second CP are generated based on the pulsePD signal, the VCOP signal, and the VCON signal. For example, CP signals are generated to control the first CP and the second CP, respectively. In some embodiments, CP signals are generated such that the CPs facilitate adjustment of a zero crossing phase of the VCON and VCOP signals with respect to the pulsePD signal. In this manner, a divider-less PLL is provided, thus mitigating PLL power consumption.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: November 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yen-Jen Chen, I-Ting Lee, Hsieh-Hung Hsieh, Chewn-Pu Jou, Fu-Lung Hsueh, Shen-Iuan Liu
  • Clock and data recovery using LC voltage controlled oscillator and delay locked loop
    Patent number: 8885787
    Abstract: A clock and data recovery (CDR) circuit includes an inductor-capacitor voltage controlled oscillator (LCVCO) configured to generate a clock signal with a clock frequency. The CDR circuit further includes a delay locked loop (DLL) configured to receive the clock signal from the LCVCO and generate multiple clock phases and a first charge pump configured to control the LCVCO. The CDR circuit further includes a phase detector configured to receive a data input and the multiple clock phases from the DLL, and to align a data edge of the data input and the multiple clock phases.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan-Hong Chern, Chih-Chang Lin, Ming-Chieh Huang, Fu-Lung Hsueh
  • CIRCUIT FOR REDUCING NEGATIVE BIAS TEMPERATURE INSTABILITY
    Publication number: 20140320169
    Abstract: A circuit comprises a control circuit having an output node. The circuit also comprises a half latch keeper circuit coupled to the control circuit. The half latch keeper circuit is configured to control the output node during a standby mode. The circuit also comprises a transistor coupled to the output node. The control circuit is configured to turn off the transistor during the standby mode.
    Type: Application
    Filed: July 15, 2014
    Publication date: October 30, 2014
    Inventors: Chan-Hong CHERN, Fu-Lung HSUEH, Ming-Chieh HUANG, Bryan SHEFFIELD, Chih-Chang LIN
  • Motion detection using capacitor having different work function materials
    Patent number: 8857260
    Abstract: An apparatus for detecting mechanical displacement in a micro-electromechanical system includes a capacitor having first and second plates spaced from one another, the first and second plates having different work functions and being electrically connected with each other. The capacitor plates are movable with respect to one another such that a spacing between the plates changes in response to a force. A current through the capacitor represents a rate of change in the spacing between the plates at a given time.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: October 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Alexander Kalnitsky, Fu-Lung Hsueh
  • Cascode CMOS structure
    Patent number: 8847321
    Abstract: A MOS device includes an active area having first and second contacts. First and second gates are disposed between the first and second contacts. The first gate is disposed adjacent to the first contact and has a third contact. The second gate is disposed adjacent to the second contact and has a fourth contact coupled to the third contact. A transistor defined by the active area and the first gate has a first threshold voltage, and a transistor defined by the active area and the second gate has a second threshold voltage.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fu-Lung Hsueh, Chih-Ping Chao, Chewn-Pu Jou, Yung-Chow Peng, Harry-Hak-Lay Chuang, Kuo-Tung Sung
  • Reconfigurable and auto-reconfigurable resonant clock
    Patent number: 8847652
    Abstract: The present disclosure relates to a resonant clock system having a driver component, a clock load capacitor, and a reconfigurable inductor array. The driver component generates a driven input signal. The clock load capacitor is configured to receive the driven input signal. The inductor array is configured to have an effective inductance according to a selected frequency. The inductor array also generates a resonant signal at the selected frequency using the effective inductance.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chan-Hong Chern, Tao Wen Chung, Chih-Chang Lin, Ming-Chieh Huang, Tsung-Ching Huang, Fu-Lung Hsueh
  • Multi-Gate and Complementary Varactors in FinFET Process
    Publication number: 20140264628
    Abstract: A varactor includes at least one semiconductor fin, a first gate, and a second gate physically disconnected from the first gate. The first gate and the second gate form a first FinFET and a second FinFET, respectively, with the at least one semiconductor fin. The source and drain regions of the first FinFET and the second FinFET are interconnected to form the varactor.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Inventors: Chi-Hsien Lin, Ying-Ta Lu, Hsien-Yuan Liao, Ho-Hsiang Chen, Chewn-Pu Jou, Fu-Lung Hsueh
  • Integrated circuits with resistors and methods of forming the same
    Patent number: 8835246
    Abstract: A method of forming an integrated circuit includes forming at least one transistor over a substrate. The at least one transistor includes a first gate dielectric structure disposed over a substrate. A work-function metallic layer is disposed over the first gate dielectric structure. A conductive layer is disposed over the work-function metallic layer. A source/drain (S/D) region is disposed adjacent to each sidewall of the first gate dielectric structure. At least one resistor structure is formed over the substrate. The at least one resistor structure includes a first doped semiconductor layer disposed over the substrate. The at least one resistor structure does not include any work-function metallic layer between the first doped semiconductor layer and the substrate.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: September 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan-Hong Chern, Fu-Lung Hsueh
  • CONTACTLESS COMMUNICATIONS USING FERROMAGNETIC MATERIAL
    Publication number: 20140256063
    Abstract: A communications structure comprises a first semiconductor substrate having a first coil, and a second semiconductor substrate having a second coil above the first semiconductor substrate. Inner edges of the first and second coils define a boundary of a volume that extends below the first coil and above the second coil. A ferromagnetic core is positioned at least partially within the boundary, such that a mutual inductance is provided between the first and second coils for wireless transmission of signals or power between the first and second coils.
    Type: Application
    Filed: May 19, 2014
    Publication date: September 11, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ping-Lin YANG, Jun-De JIN, Fu-Lung HSUEH, Sa-Lly LIU, Tong-Chern ONG, Chun-Jung LIN, Ya-Chen KAO
  • Capactive load PLL with calibration loop
    Patent number: 8816732
    Abstract: A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: August 26, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chan-Hong Chern, Tao Wen Chung, Ming-Chieh Huang, Chih-Chang Lin, Tsung-Ching Huang, Fu-Lung Hsueh
  • Built-in Self-test Circuit for Voltage Controlled Oscillator
    Publication number: 20140225676
    Abstract: A device comprises a radio frequency peak detector configured to receive an ac signal from a voltage controlled oscillator and generate a dc value proportional to the ac signal at an output of the radio frequency peak detector and a feedback control unit coupled between an output of the radio frequency peak detector and an input of the voltage controlled oscillator.
    Type: Application
    Filed: April 15, 2014
    Publication date: August 14, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsieh-Hung Hsieh, Ming Hsien Tsai, Tzu-Jin Yeh, Chewn-Pu Jou, Fu-Lung Hsueh
  • IMAGE SENSOR CONFIGURED TO REDUCE BLOOMING DURING IDLE PERIOD
    Publication number: 20140217263
    Abstract: Among other things, techniques and systems are provided for identifying when a pixel of an image sensor is in an idle period. A flag is utilized to differentiate when the pixel is in an idle period and when the pixel is in an integration period. When the flag indicates that the pixel is in an idle period, a blooming operation is performed on the pixel to reduce an amount of electrical charge that has accumulated at the pixel or to mitigate electrical charge from accumulating at the pixel. In this way, the blooming operation reduces a probability that the photosensitive sensor becomes saturated during an idle period of the pixel, and thus reduces the likelihood of electrical charge from a pixel that is not intended contribute to an image from spilling over and potentially contaminating a pixel that is intended to contribute to the image.
    Type: Application
    Filed: February 5, 2013
    Publication date: August 7, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuo-Yu Chou, Calvin Yi-Ping Chao, Jhy-Jyi Sze, Honyih Tu, Fu-Lung Hsueh
  • Circuit for reducing negative bias temperature instability
    Patent number: 8791720
    Abstract: A control circuit comprises a first NOR gate, a first NMOS transistor, and a first PMOS transistor. The control circuit also comprises an output node. The control circuit further comprises a half latch keeper circuit coupled to a gate of the first NMOS transistor and to a gate of the first PMOS transistor. The half latch keeper circuit is configured to keep the output node at a logical 1 during a standby mode. The control circuit additionally comprises an operational PMOS transistor coupled to the output node. An output of the first NOR gate is coupled to a gate of the operational PMOS transistor. The control circuit is configured to turn off the operational PMOS transistor during the standby mode.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: July 29, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan-Hong Chern, Fu-Lung Hsueh, Ming-Chieh Huang, Bryan Sheffield, Chih-Chang Lin
  • MCML RETENTION FLIP-FLOP/LATCH FOR LOW POWER APPLICATIONS
    Publication number: 20140184296
    Abstract: The present disclosure relates to a device and method to reduce the dynamic/static power consumption of an MCML logic device. In order to retain register contents during power off mode, an MCML retention latch and flip-flop are disclosed. Retention Latch circuits in MCML architecture are used to retain critical register contents during power off mode, wherein combination logic including clock buffers on the clock tree paths are powered off to reduce dynamic/static power consumption. The MCML retention flip-flop comprises a master latch and a slave latch, wherein a power switch is added to the master latch to power the master latch off during power off mode. The slave latch includes pull-down circuits that remain active to enable the slave latch to retain data at a proper voltage level during power off mode. Other devices and methods are also disclosed.
    Type: Application
    Filed: December 27, 2012
    Publication date: July 3, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsiung Lee, Shi-Hung Wang, Kuang-Kai Yen, Wei-Li Chen, Yung-Hsu Chuang, Shih-Hung Lan, Fan-Ming Kuo, Chewn-Pu Jou, Fu-Lung Hsueh
  • Contactless communications using ferromagnetic material
    Patent number: 8760255
    Abstract: A communications structure comprises a first semiconductor substrate having a first coil, and a second semiconductor substrate having a second coil above the first semiconductor substrate. Inner edges of the first and second coils define a boundary of a volume that extends below the first coil and above the second coil. A ferromagnetic core is positioned at least partially within the boundary, such that a mutual inductance is provided between the first and second coils for wireless transmission of signals or power between the first and second coils.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: June 24, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ping-Lin Yang, Jun-De Jin, Fu-Lung Hsueh, Sa-Lly Liu, Tong-Chern Ong, Chun-Jung Lin, Ya-Chen Kao
  • Semiconductor device design system and method of using the same
    Patent number: 8762897
    Abstract: A circuit design system includes a schematic design tool configured to generate schematic information and pre-coloring information for a circuit. The circuit design system also includes a netlist file configured to store the schematic information and the pre-coloring information on a non-transitory computer readable medium and an extraction tool configured to extract the pre-coloring information from the netlist file. A layout design tool, included in the circuit design system, is configured to design at least one mask based on the schematic information and the pre-coloring information. The circuit design system further includes a layout versus schematic comparison tool configured to compare the at least one mask to the schematic information and the pre-coloring information.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: June 24, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsien Chang, Yung-Chow Peng, Fu-Lung Hsueh
  • METHOD AND APPARATUS OF RFID TAG CONTACTLESS TESTING
    Publication number: 20140145749
    Abstract: A semiconductor wafer includes a plurality of dies. Each of the plurality of dies includes a radio frequency identification (RFID) tag circuit and a coil. The RFID tag circuit includes a tag core, an RF front-end circuit, an ID decoder, a comparator and conductive line for a unique ID. The RF front-end circuit is configured to receive electromagnetic signals through the coil in each of the plurality of dies and to convert the received electromagnetic signals into commands. The ID decoder is configured to receive the commands and to generate an expect ID. The comparator is configured to compare the unique ID with the expect ID to generate a comparison result. The comparison result is arranged to decide if the tag core is configured to receive commands.
    Type: Application
    Filed: June 25, 2013
    Publication date: May 29, 2014
    Inventors: Tsung-Hsiung Lee, Kuang-Kai Yen, Shi-Hung Wang, Yung-Hsu Chuang, Huan-Neng Chen, Wei-Li Chen, Shih-Hung Lan, Yi-Hsuan Liu, Fan-Ming Kuo, Hsieh-Hung Hsieh, Chewn-Pu Jou, Fu-Lung Hsueh
  • Dual-Side Illumination Image Sensor Chips and Methods for Forming the Same
    Publication number: 20140138521
    Abstract: A Dual-Side Illumination (DSI) image sensor chip includes a first image sensor chip configured to sense light from a first direction, and a second image sensor chip aligned to, and bonded to, the first image sensor chip. The second image sensor chip is configured to sense light from a second direction opposite the first direction.
    Type: Application
    Filed: November 21, 2012
    Publication date: May 22, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Min Liu, Honyih Tu, Calvin Yi-Ping Chao, Fu-Lung Hsueh