Patents by Inventor Fu Tsai

Fu Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12142499
    Abstract: A pickup apparatus for separating a semiconductor die adhered on an adhesive film therefrom includes a frame, an UV light emitting element, and a collector element. The frame is configurated to hold the adhesive film adhered with the semiconductor die thereon. The UV light emitting element is disposed inside the frame, where the adhesive film is disposed between the semiconductor die and the UV light emitting element. The collector element is disposed over the frame.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: November 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jung Chen, Tsung-Fu Tsai, Szu-Wei Lu
  • Publication number: 20240371821
    Abstract: A package structure including an interposer, at least one semiconductor die and an insulating encapsulation is provided. The interposer includes a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, the interconnect structure includes interlayer dielectric films and interconnect wirings embedded in the interlayer dielectric films, the semiconductor substrate includes a first portion and a second portion disposed on the first portion, the first interconnect structure is disposed on the second portion, and a first maximum lateral dimension of the first portion is greater than a second maximum lateral dimension of the second portion. The at least one semiconductor die is disposed over and electrically connected to the interconnect structure. The insulating encapsulation is disposed on the first portion, wherein the insulating encapsulation laterally encapsulates the least one semiconductor die and the second portion.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kung-Chen Yeh, Szu-Wei Lu, Tsung-Fu Tsai, Ying-Ching Shih
  • Publication number: 20240364788
    Abstract: A method and system for transmitting and receiving data packets between two network nodes via one or more end-to-end connections. An interface is provided for selecting one or more possible end-to-end connection(s) or established end-to-end connection(s). The method and system may further comprise receiving a policy, wherein one or more selected end-to-end connections are established based, at least in part, on the policy. The policy may also restrict or promote selection of certain established end-to-end connection(s) via the interface provided. The selected and established end-to-end connection(s) are used for transmitting and receiving data packets.
    Type: Application
    Filed: June 6, 2024
    Publication date: October 31, 2024
    Applicant: Pismo Labs Technology Limited
    Inventors: Patrick Ho Wai SUNG, Ho Ming CHAN, Kit Wai CHAU, Min-Fu TSAI
  • Publication number: 20240351155
    Abstract: The present disclosure provides a knife sharpening device, including a housing and a sharpening assembly arranged inside the housing. The sharpening assembly includes a sharpening wheel rotatably mounted inside the housing. The sharpening wheel includes two opposite mounting surfaces arranged along an axial direction and a sharpening surface along a circumferential direction. The housing is formed thereon with a first sharpening groove that is arranged on a first side of the sharpening surface. The first sharpening groove is formed with openings at both ends along a length direction, and the first side of the sharpening surface extends partially into an interior of the first sharpening groove. During sharpening, a knife is placed into the first sharpening groove to contact the sharpening surface for grinding. According to the technical solution of the present disclosure, sharpening grooves are formed on the housing and fit with the sharpening surface.
    Type: Application
    Filed: July 18, 2023
    Publication date: October 24, 2024
    Inventor: MOU-FU TSAI
  • Patent number: 12119324
    Abstract: A package structure including an interposer, at least one semiconductor die and an insulating encapsulation is provided. The interposer includes a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, the interconnect structure includes interlayer dielectric films and interconnect wirings embedded in the interlayer dielectric films, the semiconductor substrate includes a first portion and a second portion disposed on the first portion, the first interconnect structure is disposed on the second portion, and a first maximum lateral dimension of the first portion is greater than a second maximum lateral dimension of the second portion. The at least one semiconductor die is disposed over and electrically connected to the interconnect structure. The insulating encapsulation is disposed on the first portion, wherein the insulating encapsulation laterally encapsulates the least one semiconductor die and the second portion.
    Type: Grant
    Filed: October 10, 2022
    Date of Patent: October 15, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kung-Chen Yeh, Szu-Wei Lu, Tsung-Fu Tsai, Ying-Ching Shih
  • Publication number: 20240339415
    Abstract: A structure including a first semiconductor die, an interposer and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate and conductive vias disposed on the interconnect structure. The interposer includes a dielectric layer and through vias penetrating through the dielectric layer. The first insulating encapsulation laterally encapsulates the first semiconductor die and the interposer, wherein a thickness of the dielectric layer of the interposer substantially equals to a thickness of the first semiconductor die and a thickness of the first insulating encapsulation.
    Type: Application
    Filed: June 13, 2024
    Publication date: October 10, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Fu Tsai, Szu-Wei Lu
  • Patent number: 12100702
    Abstract: A method of making a semiconductor device includes manufacturing doped zones in a first semiconductor material over a substrate. The method further includes forming an isolation structure between adjacent doped zones of the first semiconductor material. The method further includes manufacturing lines extending in a first direction over the doped zones of the first semiconductor material, wherein each of the lines has a line width measured along a second direction perpendicular to the first direction. The method further includes trimming the lines into line segments having ends over the isolation structure. The method further includes etching a transistor gate electrode over the substrate, wherein transistor gate electrode has a gate electrode width measured along the second direction, and wherein the line width is substantially similar to the gate electrode width.
    Type: Grant
    Filed: October 18, 2023
    Date of Patent: September 24, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Li-Wei Chu, Wun-Jie Lin, Yu-Ti Su, Ming-Fu Tsai, Jam-Wem Lee
  • Publication number: 20240306762
    Abstract: An insole combination, comprising an inner insole, an outer insole, and at least one stimulating medium. The inner insole has a plurality of first engaging portions, one upper surface, and a plurality of mark regions, which respectively correspond to a plurality of plantar reflexology areas. The outer insole has a plurality of second engaging portions, and the inner insole is accommodated in the outer insole. The stimulating medium is accommodated between the inner insole and the outer insole, and has one first holding end and one second stimulation end to perform a stimulating effect on the pelma.
    Type: Application
    Filed: January 25, 2022
    Publication date: September 19, 2024
    Applicant: TAOBODY LIFETIME HEALTHINESS, INC.
    Inventor: Ching-Fu TSAI
  • Publication number: 20240304466
    Abstract: A method of fabricating a semiconductor device is provided. The method includes providing a die stacking unit that includes a plurality of dies stacked on each other, and a plurality of conductive joints connected between each two adjacent dies. The method includes providing a plurality of dummy micro bumps and dummy pads between the two adjacent dies and between the conductive joints. The dummy micro bumps and the dummy pads are connected to one of the two adjacent dies but not to the other, and the dummy micro bumps are formed on some of the dummy pads but not on all of the dummy pads. The method includes dispensing an underfill material into gaps between the plurality of dies, the conductive joints, the dummy micro bumps, and the dummy pads.
    Type: Application
    Filed: May 20, 2024
    Publication date: September 12, 2024
    Inventors: Tsung-Fu TSAI, Chen-Hsuan TSAI, Chung-Chieh TING, Shih-Ting LIN, Szu-Wei LU
  • Patent number: 12085244
    Abstract: A light string includes a housing, a light cap, and a light assembly. The light cap has a cap body, an upper tip at an upper end of the cap body, and a peripheral visibility ring extending outwardly from the cap body opposite the upper tip. The light cap is coupled to and extends from the housing such that the peripheral visibility ring seats adjacent to an end of the housing proximate the light aperture. The light assembly includes a light emitting source that is positioned such that when energized, light is emitted that is visible from outside the light cap. Moreover, the peripheral visibility ring reflects light in a direction different from the light emitted by the light emitting source such that the light emitted by the light emitting source is visible when an observer is looking at a side view of the cap body.
    Type: Grant
    Filed: August 24, 2023
    Date of Patent: September 10, 2024
    Inventor: Chang Fu Tsai
  • Publication number: 20240280764
    Abstract: A method includes connecting a photonic package to a substrate, wherein the photonic package includes a waveguide and an edge coupler that is optically coupled to the waveguide; connecting a semiconductor device to the substrate adjacent the photonic package; depositing a first protection material on a first sidewall of the photonic package that is adjacent the edge coupler; encapsulating the photonic package and the semiconductor device with an encapsulant; performing a first sawing process through the encapsulant and the substrate, wherein the first sawing process exposes the first protection material; and removing the first protection material to expose the first sidewall of the photonic package.
    Type: Application
    Filed: August 2, 2023
    Publication date: August 22, 2024
    Inventors: Tsung-Fu Tsai, Chen-Hua Yu, Szu-Wei Lu, Chao-Jen Wang
  • Publication number: 20240281209
    Abstract: A machine learning optimization circuit and a method thereof are provided. The method includes steps of: generating a local feature matrix from an extraction range in a feature tensor matrix, and the local feature matrix includes feature values of X columns, Y rows, and Z channels; partitioning W sub-feature matrices from the local feature matrix, and each of the W sub-feature matrices includes X×Y×Z/W feature values; simultaneously performing parallel dot product operations on the W sub-feature matrices by W×K parallel operation modules to generate W×K temporary feature matrices; and integrating the W×K temporary feature matrices into a local feature output matrix corresponding to the local feature matrix, and the local feature output matrix includes feature values of X columns, Y rows, and Z channels.
    Type: Application
    Filed: July 25, 2023
    Publication date: August 22, 2024
    Inventors: Chieh-Fu TSAI, Chia-Hsiang YANG, Cheng-Yan DU
  • Publication number: 20240272352
    Abstract: A method includes connecting a first photonic package to a substrate, wherein the first photonic package includes a first waveguide and a first support over the first waveguide; connecting a second photonic package to the substrate adjacent the first photonic package, wherein the second photonic package includes a second waveguide, wherein the first photonic package and the second photonic package are laterally separated by a gap that has a width in the range of 15 ?m to 190 ?m; depositing a first quantity of an optical adhesive into the gap; and curing the first quantity of the optical adhesive, wherein after curing the first quantity of the optical adhesive, the first waveguide is optically coupled to the second waveguide through the first quantity of the optical adhesive.
    Type: Application
    Filed: May 26, 2023
    Publication date: August 15, 2024
    Inventors: Chen-Hua Yu, Tsung-Fu Tsai, Chih-Hao Yu, Jui Lin Chao, Szu-Wei Lu
  • Publication number: 20240272616
    Abstract: A control method applied to a servomotor, wherein the servomotor includes a motor, and the control method includes: setting a mode of the servomotor as a predetermined mode corresponding to a predetermined communication protocol; receiving an input signal from a controller for controlling the motor, wherein the controller is coupled to the servomotor; and switching the mode of the servomotor from the predetermined mode to one of a plurality of candidate modes according to a frequency of the input signal.
    Type: Application
    Filed: February 15, 2023
    Publication date: August 15, 2024
    Applicant: Elite Semiconductor Microelectronics Technology Inc.
    Inventors: Ming-Fu Tsai, Sheng-Hung Hsu
  • Patent number: 12051896
    Abstract: A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. When the first transistor is turned on by a detection signal, the first transistor is turned off.
    Type: Grant
    Filed: May 24, 2023
    Date of Patent: July 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin Peng, Yu-Ti Su, Chia-Wei Hsu, Ming-Fu Tsai, Shu-Yu Su, Li-Wei Chu, Jam-Wem Lee, Chia-Jung Chang, Hsiang-Hui Cheng
  • Patent number: 12046561
    Abstract: A structure including a first semiconductor die, an interposer and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate and conductive vias disposed on the interconnect structure. The interposer includes a dielectric layer and through vias penetrating through the dielectric layer. The first insulating encapsulation laterally encapsulates the first semiconductor die and the interposer, wherein a thickness of the dielectric layer of the interposer substantially equals to a thickness of the first semiconductor die and a thickness of the first insulating encapsulation.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: July 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Fu Tsai, Szu-Wei Lu
  • Publication number: 20240241560
    Abstract: A computing device permits distribution of power received from an external power source to one or more subsystems of the computing device. The computing device receives input requesting a power control operation and, responsive to the input, interrupts the distribution of the power to at least one of the subsystems.
    Type: Application
    Filed: January 16, 2023
    Publication date: July 18, 2024
    Inventors: Hsuan Wei-Yi, Yi-Hsin Huang, Ying-Chi Chou, Wen-Fu Tsai
  • Patent number: 12034811
    Abstract: A method and system for transmitting and receiving data packets between two network nodes via one or more end-to-end connections. An interface is provided for selecting one or more possible end-to-end connection(s) or established end-to-end connection(s). The method and system may further comprise receiving a policy, wherein one or more selected end-to-end connections are established based, at least in part, on the policy. The policy may also restrict or promote selection of certain established end-to-end connection(s) via the interface provided. The selected and established end-to-end connection(s) are used for transmitting and receiving data packets.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: July 9, 2024
    Assignee: Pismo Labs Technology Limited
    Inventors: Patrick Ho Wai Sung, Ho Ming Chan, Kit Wai Chau, Min-Fu Tsai
  • Publication number: 20240222363
    Abstract: A semiconductor device includes a first diode, a second diode, a clamp circuit and a third diode. The first diode is coupled between an input/output (I/O) pad and a first voltage terminal. The second diode is coupled with the first diode, the I/O pad and a second voltage terminal. The clamp circuit is coupled between the first voltage terminal and the second voltage terminal. The second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (ESD) current flowing between the I/O pad and the first voltage terminal. The third diode, coupled to the first voltage terminal, and the second diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal.
    Type: Application
    Filed: March 14, 2024
    Publication date: July 4, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin PENG, Li-Wei CHU, Ming-Fu TSAI, Jam-Wem LEE, Yu-Ti SU
  • Patent number: 12020952
    Abstract: A method of fabricating a semiconductor device is provided, including providing a base substrate and a die stacking unit mounted on the base substrate. Conductive joints are connected between two adjacent dies of the die stacking unit. The method further includes providing dummy micro bumps and dummy pads between the two adjacent dies and between the conductive joints. The dummy micro bumps and the dummy pads are connected to one of the two adjacent dies but not to the other, and the dummy micro bumps are formed on some of the dummy pads but not on all of the dummy pads. In addition, the method includes filling the gaps between the base substrate, all dies of the die stacking unit, the conductive joints, the dummy micro bumps, and the dummy pads with an underfill material by capillary attraction.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: June 25, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Fu Tsai, Chen-Hsuan Tsai, Chung-Chieh Ting, Shih-Ting Lin, Szu-Wei Lu