Patents by Inventor Fu Tsai

Fu Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230417993
    Abstract: A package includes a laser diode includes a bonding layer; a first dielectric layer over the laser diode, wherein the first dielectric layer is directly bonded to the bonding layer of the laser diode; a first silicon nitride waveguide in the first dielectric layer, wherein the first silicon nitride waveguide extends over the laser diode; a second dielectric layer over the first silicon nitride waveguide; a silicon waveguide in the second dielectric layer; an interconnect structure over the silicon waveguide; and conductive features extending through the first dielectric layer and the second dielectric layer to electrically contact the interconnect structure.
    Type: Application
    Filed: June 27, 2022
    Publication date: December 28, 2023
    Inventors: Tsung-Fu Tsai, Hsing-Kuo Hsia, Szu-Wei Lu, Chen-Hua Yu
  • Patent number: 11855452
    Abstract: An ESD power clamp device includes an ESD detection circuit; a controlling circuit coupled with the ESD detection circuit; a field effect transistor (FET) coupled with the controlling circuit, and an impedance element coupled with the FET. The FET includes a drain terminal coupled with a first supply node; a gate terminal coupled with the controlling circuit; a source terminal coupled with a second supply node via the impedance element; and a bulk terminal coupled with second supply node.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ken-Hao Fan, Yu-Ti Su, Tzu-Cheng Kao, Ming-Fu Tsai, Chia-Lin Hsu
  • Patent number: 11854984
    Abstract: A semiconductor package includes a first semiconductor die, a second semiconductor die, a semiconductor bridge, an integrated passive device, a first redistribution layer, and connective terminals. The second semiconductor die is disposed beside the first semiconductor die. The semiconductor bridge electrically connects the first semiconductor die with the second semiconductor die. The integrated passive device is electrically connected to the first semiconductor die. The first redistribution layer is disposed over the semiconductor bridge. The connective terminals are disposed on the first redistribution layer, on an opposite side with respect to the semiconductor bridge. The first redistribution layer is interposed between the integrated passive device and the connective terminals.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hsuan Tsai, Chin-Chuan Chang, Szu-Wei Lu, Tsung-Fu Tsai
  • Patent number: 11855060
    Abstract: A package structure includes a circuit substrate, a semiconductor package, a lid structure and a plurality of first spacer structures. The semiconductor package is disposed on and electrically connected to the circuit substrate. The lid structure is disposed on the circuit substrate covering the semiconductor package, wherein the lid structure is attached to the circuit substrate through an adhesive material. The plurality of first spacer structures is surrounding the semiconductor package, wherein the first spacer structures are sandwiched between the lid structure and the circuit substrate, and includes a top portion in contact with the lid structure and a bottom portion in contact with the circuit substrate.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Fu Tsai, Chin-Fu Kao, Pu Wang, Szu-Wei Lu
  • Patent number: 11848554
    Abstract: An electrostatic discharge (ESD) circuit includes an ESD detection circuit, a clamp circuit and an ESD assist circuit. The ESD detection circuit is coupled between a first and a second node. The first node has a first voltage. The second node has a second voltage. The clamp circuit includes a first transistor having a first gate, a first drain, a first source and a first body terminal. The first gate is coupled to at least the ESD detection circuit by a third node. The first drain is coupled to the second node. The first source and the first body terminal are coupled together at the first node. The ESD assist circuit is coupled between the first node and the third node, and is configured to clamp a third voltage of the third node at the first voltage during an ESD event at the first node or the second node.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: December 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Lin Hsu, Ming-Fu Tsai, Yu-Ti Su, Kuo-Ji Chen
  • Publication number: 20230402345
    Abstract: A semiconductor package including a cooling system and a method of forming are provided. The semiconductor package may include an interposer, one or more package components bonded to the interposer, an encapsulant on the interposer, and a cooling system over the one or more package components. The cooling system may include one or more metal layers on top surfaces of the one or more package components, first metal pins on the one or more metal layers, second metal pins, wherein each of the second metal pins may be bonded to a corresponding one of the first metal pins by solder, and a first lid over the second metal pins, wherein the first lid may include openings.
    Type: Application
    Filed: June 13, 2022
    Publication date: December 14, 2023
    Inventors: Chen Chiang Yu, Tsung-Fu Tsai, Szu-Wei Lu
  • Publication number: 20230402346
    Abstract: A device includes a package substrate, an interposer having a first side bonded to the package substrate, a first die bonded to a second side of the interposer, the second side being opposite the first side, a ring on the package substrate, where the ring surrounds the first die and the interposer, a molding compound disposed between the ring and the first die, where the molding compound is in physical contact with the ring, and a plurality of thermal-conductive layers over and in physical contact with the molding compound and the first die, where the molding compound is disposed between the plurality of thermal-conductive layers and the ring.
    Type: Application
    Filed: June 10, 2022
    Publication date: December 14, 2023
    Inventors: Szu-Wei Lu, Tsung-Fu Tsai, Chi-Hsiang Chen
  • Patent number: 11837598
    Abstract: A semiconductor device includes a first doped zone and a second doped zone in a first semiconductor material, the first doped zone being separated from the second doped zone; an isolation structure between the first doped zone and the second doped zone; and a first line segment over a top surface of the first doped zone, where the ends of the first line segment and the ends of the second line are over the isolation structure. The first line segment and the second line segment have a first width; and a dielectric material is between the first line segment and the second line segment and over the isolation structure. The first width is substantially similar to a width of a gate electrode in the semiconductor device.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: December 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Li-Wei Chu, Wun-Jie Lin, Yu-Ti Su, Ming-Fu Tsai, Jam-Wem Lee
  • Publication number: 20230369370
    Abstract: A package structure includes an optical die, an optical die, a supporting structure, and a lens structure. The optical die includes a photonic region. The optical die is disposed on and electrically coupled to the optical die. The supporting structure is disposed on the optical die, where the electric die is disposed between the supporting structure and the optical die. The lens structure is disposed on the supporting structure and optically coupled to the photonic region of the optical die, where the supporting structure is disposed between the lens structure and the electric die.
    Type: Application
    Filed: May 13, 2022
    Publication date: November 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jung Chen, Tsung-Fu Tsai, Szu-Wei Lu, Wei-An Tsao, Che-Yuan Yang, Chien-Ting Chen, Chih-Chieh Hung
  • Patent number: 11817425
    Abstract: A package structure is provided. The package structure includes a substrate and a stack of semiconductor dies over the substrate. The package structure also includes an underfill element covering sidewalls of the semiconductor dies. The package structure further includes a protective film attached to the substrate and laterally surrounding the underfill element and the semiconductor dies. The underfill element separates the protective film from the semiconductor dies.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: November 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hsuan Tsai, Tsung-Fu Tsai, Shih-Ting Lin, Szu-Wei Lu
  • Publication number: 20230361052
    Abstract: A package structure includes a redistribution circuit structure, a wiring substrate, an insulating encapsulation, and a reinforcement structure. The redistribution circuit structure has dielectric layers. The wiring substrate is disposed on the redistribution circuit structure. The insulating encapsulation laterally encapsulates the wiring substrate. The reinforcement structure includes reinforcement pattern layers and reinforcement vias. The reinforcement pattern layers and the dielectric layers are stacked alternately. The reinforcement vias penetrate through the dielectric layers to connect the reinforcement pattern layers. At least one of the reinforcement pattern layers is embedded in the insulating encapsulation. The reinforcement structure is electrically floating.
    Type: Application
    Filed: July 18, 2023
    Publication date: November 9, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Fu Tsai, Shih-Ting Lin, Szu-Wei Lu, Chen-Hsuan Tsai, I-Ting Huang
  • Publication number: 20230352338
    Abstract: Methods and devices are provided herein for enhancing robustness of a bipolar electrostatic discharge (ESD) device. The robustness of a bipolar ESD device includes providing an emitter region and a collector region adjacent to the emitter region. An isolation structure is provided between the emitter region and the collector region. A ballasting characteristic at the isolation structure is modified by inserting at least one partition structure therein. Each partition structure extends substantially abreast at least one of the emitter and the collector regions.
    Type: Application
    Filed: July 3, 2023
    Publication date: November 2, 2023
    Inventors: Alexander Kalnitsky, Jen-Chou Tseng, Chia-Wei Hsu, Ming-Fu Tsai
  • Publication number: 20230346639
    Abstract: A health care device includes a health care body for positioning a body part of a user, so as to maintain a first specific positional relationship with the body part, wherein the body part has an acupoint; an acupoint work piece for performing a health care work onto the use through the acupoint; and a work piece holder having a first end connected to the health care body and a second end for fixing the acupoint work piece, so that under the first specific positional relationship, the acupoint work piece performs the health care work under the condition that the acupoint work piece has a second specific positional relationship with the acupoint. A health care body, method and system are also provided.
    Type: Application
    Filed: August 24, 2022
    Publication date: November 2, 2023
    Applicant: TAO MINING CO., LTD.
    Inventor: Ching-Fu TSAI
  • Publication number: 20230343743
    Abstract: A flip-chip bonding method includes following operations. A wafer is provided with multiple semiconductor dies on an adhesive film held by a frame element. A semiconductor die is lifted up from the wafer by an ejector element. The semiconductor die is picked up with a collector element. The semiconductor die is flip-chipped with the collector element. An alignment check is performed to determine a position of the semiconductor die, so as to determine a process tolerance between a center of the collector element and a center of the semiconductor die. The semiconductor die with the collector element is transferred to a location underneath a bonder element based on the process tolerance of the alignment check. The semiconductor die is picked up from the collector element by the bonder element. The semiconductor die is bonded to a carrier by the bonder element.
    Type: Application
    Filed: April 21, 2022
    Publication date: October 26, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jung Chen, Tsung-Fu Tsai, Szu-Wei Lu
  • Publication number: 20230317564
    Abstract: A semiconductor package includes a first integrated circuit, a plurality of first through vias and a plurality of fin-shaped through vias. The first through vias surround the first integrated circuit. The fin-shaped through vias are physically connected to the first through vias respectively, wherein the first through vias are disposed between the first integrated circuit and the fin-shaped through vias.
    Type: Application
    Filed: April 1, 2022
    Publication date: October 5, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jung Chen, Wei-An Tsao, Tsung-Fu Tsai, Szu-Wei Lu
  • Patent number: 11777424
    Abstract: A method for determining an initial rotor position of a permanent magnet synchronous motor (PMSM) includes: generating a plurality of transient currents by applying a plurality of voltages to each phase stator winding of a three phase stator winding of the PMSM; generating three phase current differences according to the plurality of transient currents; determining a first zone in which the initial rotor position of the PMSM is located according to the three phase current differences, wherein angles between 0-360 degrees are divided into a plurality of zones, and the first zone is selected from the plurality of zones; calculating three line current differences according to the three phase current differences; and determining the initial rotor position of the PMSM according to the first zone and the three line current differences.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: October 3, 2023
    Assignee: Elite Semiconductor Microelectronics Technology Inc.
    Inventors: Shih-Chieh Wang, Yong-Yi Jhuang, Ming-Fu Tsai
  • Patent number: 11769739
    Abstract: A package structure includes a redistribution circuit structure, a wiring substrate, a semiconductor device, an insulating encapsulation, and a reinforcement structure. The redistribution circuit structure has dielectric layers. The wiring substrate is disposed on the redistribution circuit structure. The semiconductor device is disposed on the redistribution circuit structure opposite to the wiring substrate. The insulating encapsulation laterally encapsulates the wiring substrate. The reinforcement structure is partially embedded in the redistribution circuit structure and is partially embedded in the insulating encapsulation. The reinforcement structure includes reinforcement pattern layers and reinforcement vias. The reinforcement pattern layers and the dielectric layers are stacked alternately. The reinforcement vias penetrate through the dielectric layers to connect the reinforcement pattern layers. The reinforcement structure is electrically floating.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: September 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Fu Tsai, Shih-Ting Lin, Szu-Wei Lu, Chen-Hsuan Tsai, I-Ting Huang
  • Patent number: 11770080
    Abstract: A method for increasing a resolution by N bits performed by a processing circuit of a motor driving system, where N is a positive integer, and the method includes: performing a conversion upon an analog command, to generate a command count value; performing a first N-bit right-shifting operation upon the command count value, to generate an initial output value; performing a logical operation upon the command count value, to generate a low bit value; generating an overflow value according to the low bit value; and determining a final output value according to the initial output value and the overflow value.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: September 26, 2023
    Assignee: Elite Semiconductor Microelectronics Technology Inc.
    Inventor: Ming-Fu Tsai
  • Publication number: 20230298917
    Abstract: An inspection apparatus for inspecting a semiconductor workpiece includes a testing stage, a first seal member, a testing clamp, a second seal member, a semiconductor workpiece, and a transducer. The testing stage has a cavity. The first seal member is disposed in the cavity. The first seal member is attached to a sidewall of the cavity. The testing clamp is movably coupled to the testing stage. The second seal member is attached to the testing clamp. The semiconductor workpiece is held between the testing stage and the testing clamp by the first seal member and the second seal member. The transducer is movably disposed above the testing stage.
    Type: Application
    Filed: March 16, 2022
    Publication date: September 21, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Fu Tsai, Szu-Wei Lu
  • Wok
    Patent number: D1005771
    Type: Grant
    Filed: June 15, 2022
    Date of Patent: November 28, 2023
    Assignee: KAYEE INTERNATIONAL HOLDING CO., LTD.
    Inventor: Mou-Fu Tsai