Abstract: A method for determining zero crossing occurrence in an alternating current (AC) signal with constant frequency of a permanent magnet synchronous motor (PMSM) includes: sampling the AC signal to obtain a plurality of data points; starting to count a number of consecutive data points that have sampled values with a same sign in a detection range, to generate a count value, wherein the consecutive data points are included in the plurality of data points; determining whether the count value is equal to a zero crossing determination value; and in response to the count value being equal to the zero crossing determination value, determining that a zero crossing occurs at a last data point of the consecutive data points.

Abstract: A structure including a substrate having a conductive pad and a connecting structure disposed on the conductive pad and electrically connected to the conductive pad. The connecting structure includes a first metallic layer disposed on the conductive pad, a first intermetallic compound layer disposed on the first metallic layer, a second intermetallic compound layer disposed on the first intermetallic compound layer and a second metallic layer disposed on the second intermetallic compound layer. The first metallic layer comprises copper. The first intermetallic compound layer comprises a first intermetallic compound. The second intermetallic compound layer comprises a second intermetallic compound different from the first intermetallic compound. The second metallic layer comprises tin. The first intermetallic compound contains copper, tin and one of nickel and cobalt.

Abstract: A package structure including an interposer, at least one semiconductor die and an insulating encapsulation is provided. The interposer includes a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, the interconnect structure includes interlayer dielectric films and interconnect wirings embedded in the interlayer dielectric films, the semiconductor substrate includes a first portion and a second portion disposed on the first portion, the first interconnect structure is disposed on the second portion, and a first maximum lateral dimension of the first portion is greater than a second maximum lateral dimension of the second portion. The at least one semiconductor die is disposed over and electrically connected to the interconnect structure. The insulating encapsulation is disposed on the first portion, wherein the insulating encapsulation laterally encapsulates the least one semiconductor die and the second portion.

Abstract: A circuit is provided for providing a sampling clock to de-serializers in a communication physical layer. The circuit includes a slave delay lock loop (DLL), to receive an input clock and provide the sampling clock to the de-serializers. Further, a master DLL is included for receiving the input clock and outputting a control signal to the slave DLL to adjust a delay amount of the sampling clock of the slave DLL. The master DLL replicates a circuit of the slave DLL with a loop detection and determines the control signal for output.

Abstract: A package structure is provided. The package structure includes a through substrate via structure, a first stacked die package structure, an underfill layer, and a package layer. The through substrate via structure is formed over a substrate. The first stacked die package structure is over the through substrate via structure. The first stacked die package structure includes a plurality of memory dies. The underfill layer is over the first stacked die package structure. The underfill layer includes a first protruding portion that extends below a top surface of the through substrate via structure. The package layer is over the underfill layer. The package layer has a second protruding portion that extends below the top surface of the through substrate via structure.

Abstract: The present technology provides a hard-anodized pan that has a steel induction plate and a hybrid coating composition of round ceramic particles. The pan is formed of aluminum with an induction plate affixed. The aluminum is formed into the desired pan shape. The aluminum is sandblasted with beads of a particular size. The sandblasted pan is hard-anodized. The pan is coated with a hybrid coating of round ceramic particles to provide scratch-resistance and a non-stick quality. The pan is coated with a non-stick topcoat.

Abstract: A method for operating a health-care device is disclosed. The proposed method includes steps of coaxially aligning a central opening of a bottom retainer and a specific part or an acupoint of a user's body, causing a positioning device positioned on the user's body, causing a working body mounted on the bottom retainer, and operating a working piece to form a working, relation between the working end and the acupoint or the specific part, and a positional relation therebetween.

Abstract: The present disclosure provides a dual-lens movement control method, which includes steps as follows. The tracking target is detected through the wide-angle lens, and the final tracking range is calculated; the magnification and the position are determined according to the final tracking range; the separate mode or the alignment mode is determined according to the magnification and the position.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, an encapsulant, a protection layer and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The encapsulant is disposed over the interposer and laterally encapsulating the at least one semiconductor die. The connectors are disposed on the second surface of the interposer and electrically connected with the at least one semiconductor die through the interposer. The protection layer is disposed on the second surface of the interposer and surrounding the connectors. The sidewalls of the interposer include slanted sidewalls connected to the second surface, and the protection layer is in contact with the slant sidewalls of the interposer.

Abstract: An electrostatic discharge (ESD) protection circuit is coupled between first and second power supply buses. The ESD protection circuit includes a detection circuit; a pull-up circuit, coupled to the detection circuit, comprising at least a first n-type transistor; a pull-down circuit, coupled to the pull-up circuit, comprising at least a second n-type transistor; and a bypass circuit, coupled to the pull-up and pull-down circuits, wherein the detection circuit is configured to detect whether an ESD event is present on either the first or the second bus so as to cause the pull-up and pull-down circuits to selectively enable the bypass circuit for providing a discharging path between the first and second power supply buses.

Abstract: A health-care device includes a work piece having an operating end and a opposite working end to perform a health-care work on a specific part or an acupoint of a body part of a user; a work body at its lower part the operating end is mounted so that a specific working relationship between the working end and the specific part or the acupoint is maintained; and a device positioning piece connected to the work body for maintaining a specific positional relationship between the working end and the specific part or the acupoint.

Abstract: A multi-processor system performs thermal-aware task scheduling and task migration. Based on temperature measurements, the system determines one or more thermal conditions of each processor. The thermal conditions include a present temperature, a historical temperature, a predicted temperature, and thermal headroom of the processor. A scheduler identifies a target processor among the processors based on, at least in part, the one or more thermal conditions of each processor, and assigns a task to be executed by the target processor. For task migration, the system detects that a source processor satisfies a task migration criterion by comparing one or more of the thermal conditions of the source processor with corresponding thresholds. The scheduler identifies a target processor based on, at least in part, one or more of the thermal conditions of each processor, and migrates a task from the source processor to the target processor for execution.

Abstract: A package structure includes a circuits substrate, a semiconductor package, a lid structure and a plurality of first spacer structures. The semiconductor package is disposed on and electrically connected to the circuit substrate. The lid structure is disposed on the circuit substrate covering the semiconductor package, wherein the lid structure is attached to the circuit substrate through an adhesive material. The plurality of first spacer structures is surrounding the semiconductor package, wherein the first spacer structures are sandwiched between the lid structure and the circuit substrate, and includes a top portion in contact with the lid structure and a bottom portion in contact with the circuit substrate.

Abstract: A structure including a first semiconductor die, an interposer and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate and conductive vias disposed on the interconnect structure. The interposer includes a dielectric layer and through vias penetrating through the dielectric layer. The first insulating encapsulation laterally encapsulates the first semiconductor die and the interposer, wherein a thickness of the dielectric layer of the interposer substantially equals to a thickness of the first semiconductor die and a thickness of the first insulating encapsulation.

Abstract: A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. A first terminal of the first transistor is configured to receive a reference voltage signal, a control terminal of the first transistor is configured to receive a detection signal in response to an ESD event being detected, a second terminal of the first transistor is coupled to a control terminal of the third transistor, and a control terminal of the second transistor is configured to receive the logic control signal.

Abstract: A package structure includes a redistribution circuit structure, a wiring substrate, a semiconductor device, an insulating encapsulation, and a reinforcement structure. The redistribution circuit structure has dielectric layers. The wiring substrate is disposed on the redistribution circuit structure. The semiconductor device is disposed on the redistribution circuit structure opposite to the wiring substrate. The insulating encapsulation laterally encapsulates the wiring substrate. The reinforcement structure is partially embedded in the redistribution circuit structure and is partially embedded in the insulating encapsulation. The reinforcement structure includes reinforcement pattern layers and reinforcement vias. The reinforcement pattern layers and the dielectric layers are stacked alternately. The reinforcement vias penetrate through the dielectric layers to connect the reinforcement pattern layers. The reinforcement structure is electrically floating.

Abstract: A controller for a power converter includes: a first sense terminal and a second sense terminal for sensing an output voltage of the power converter; a bridging circuit configured to electrically couple the first sense terminal to the second sense terminal in a first state and electrically decouple the first sense terminal from the second sense terminal in a second state; and control circuitry configured to set the bridging circuit in the first state during a portion of a voltage ramp of the power converter, and to determine whether an open or short fault condition is present at either the first sense terminal or the second sense terminal based on a voltage across the bridging circuit in the first state.

Abstract: An electrostatic discharge (ESD) protection circuit is coupled between first and second power supply buses. The ESD protection circuit includes a detection circuit; a pull-up circuit, coupled to the detection circuit, comprising at least a first n-type transistor; a pull-down circuit, coupled to the pull-up circuit, comprising at least a second n-type transistor; and a bypass circuit, coupled to the pull-up and pull-down circuits, wherein the detection circuit is configured to detect whether an ESD event is present on either the first or the second bus so as to cause the pull-up and pull-down circuits to selectively enable the bypass circuit for providing a discharging path between the first and second power supply buses.

Abstract: A method and system for transmitting and receiving data packets between two network nodes via one or more end-to-end connections. An interface is provided for selecting one or more possible end-to-end connection(s) or established end-to-end connection(s). The method and system may further comprise receiving a policy, wherein one or more selected end-to-end connections are established based, at least in part, on the policy. The policy may also restrict or promote selection of certain established end-to-end connection(s) via the interface provided. The selected and established end-to-end connection(s) are used for transmitting and receiving data packets.

Abstract: A circuit is provided for providing a sampling clock to de-serializers in a communication physical layer. The circuit includes a slave delay lock loop (DLL), to receive an input clock and provide the sampling clock to the de-serializers. Further, a master DLL is included for receiving the input clock and outputting a control signal to the slave DLL to adjust a delay amount of the sampling clock of the slave DLL. The master DLL replicates a circuit of the slave DLL with a loop detection and determines the control signal for output.