Abstract: A semiconductor device includes a first semiconductor die and a second semiconductor die connected to the first semiconductor die. Each of the first semiconductor die and the second semiconductor die includes a substrate, a conductive bump formed on the substrate and a conductive contact formed on the conductive bump. The conductive contact has an outer lateral sidewall, there is an inner acute angle included between the outer lateral sidewall and the substrate is smaller than 85°, and the conductive contact of the first semiconductor die is connected opposite to the conductive contact of the second semiconductor die.

Abstract: A semiconductor device includes a first diode, a second diode, a clamp circuit and a third diode. The first diode is coupled between an input/output (I/O) pad and a first voltage terminal. The second diode is coupled with the first diode, the I/O pad and a second voltage terminal. The clamp circuit is coupled between the first voltage terminal and the second voltage terminal. The second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (ESD) current flowing between the I/O pad and the first voltage terminal. The third diode, coupled to the first voltage terminal, and the second diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal.

Abstract: An electrostatic discharge (ESD) circuit includes a first ESD detection circuit, a first discharging circuit and a first ESD assist circuit. The first ESD detection circuit is coupled between a first node having a first voltage and a second node having a second voltage. The first discharging circuit includes a first transistor. The first transistor has a first gate, a first drain, a first source and a first body terminal. The first gate is coupled to the first ESD detection circuit by a third node. The first drain is coupled to the first node. The first source and the first body terminal are coupled together at the second node. The first ESD assist circuit is coupled between the second and third node, and configured to clamp a third voltage of the third node at the second voltage during an ESD event at the first or second node.

Abstract: A package structure and a formation method are provided. The method includes providing a semiconductor substrate and bonding a first chip structure on the semiconductor substrate through metal-to-metal bonding and dielectric-to-dielectric bonding. The method also includes bonding a second chip structure over the semiconductor substrate through solder-containing bonding structures. The method further includes forming a protective layer surrounding the second chip structure. A portion of the protective layer is between the semiconductor substrate and a bottom of the second chip structure.

Abstract: A package structure is provided. The package structure includes a through substrate via structure, a first stacked die package structure, an underfill layer, and a package layer. The through substrate via structure is formed over a substrate. The first stacked die package structure is over the through substrate via structure, wherein the first stacked die package structure comprises a plurality of memory dies. The underfill layer is over the first stacked die package structure. the package layer is over the underfill layer, wherein the package layer has a protruding portion that extends below a top surface of the through substrate via structure.

Abstract: A semiconductor package includes a first semiconductor die, a second semiconductor die, a semiconductor bridge, an integrated passive device, a first redistribution layer, and connective terminals. The second semiconductor die is disposed beside the first semiconductor die. The semiconductor bridge electrically connects the first semiconductor die with the second semiconductor die. The integrated passive device is electrically connected to the first semiconductor die. The first redistribution layer is disposed over the semiconductor bridge. The connective terminals are disposed on the first redistribution layer, on an opposite side with respect to the semiconductor bridge. The first redistribution layer is interposed between the integrated passive device and the connective terminals.

Abstract: In some embodiments, a semiconductor device is provided, including a first doped region of a first conductivity type configured as a first terminal of a first diode, a second doped region of a second conductivity type configured as a second terminal of the first diode, wherein the first and second doped regions are coupled to a first voltage terminal; a first well of the first conductivity type surrounding the first and second doped regions in a layout view; a third doped region of the first conductivity type configured as a first terminal, coupled to an input/output pad, of a second diode; and a second well of the second conductivity type surrounding the third doped region in the layout view. The second and third doped regions, the first well, and the second well are configured as a first electrostatic discharge path between the I/O pad and the first voltage terminal.

Abstract: A package structure includes a package substrate, a first semiconductor package and a second semiconductor package, an underfill material, a gap filling structure and a heat dissipation structure. The first semiconductor package and the second semiconductor package are electrically bonded to the package substrate. The underfill material is disposed to fill a first space between the first semiconductor package and the package substrate and a second space between the second semiconductor package and the package substrate. The gap filling structure is disposed over the package substrate and in a first gap laterally between the first semiconductor package and the second semiconductor package. The heat dissipation structure is disposed on the package substrate and attached to the first semiconductor package and the second semiconductor package through a thermal conductive layer.

Abstract: In an embodiment, a device bonding apparatus is provided. The device bonding apparatus includes a first process station configured to receive a wafer; a first bond head configured to carry a die to the wafer, wherein the first bonding head includes a first rigid body and a vacuum channel in the first rigid body for providing an attaching force for carrying the die to the wafer; and a second bond head configured to press the die against the wafer, the second bond head including a second rigid body and an elastic head disposed over the second rigid body for pressing the die, the elastic head having a center portion and an edge portion surrounding the center portion, the center portion of the elastic head having a first thickness, the edge portion of the elastic head having a second thickness, the second thickness being greater than the second thickness.

Abstract: A method for forming a semiconductor device is provided. The method includes providing a wafer with multiple semiconductor dies on the adhesive film held by the frame element. The method also includes lifting a semiconductor die up from the wafer using an ejector element. The method includes picking up the semiconductor die with a collector element. The method further includes flip-chipping the semiconductor die with the collector element, and picking up the semiconductor die from the collector element using a bond-head element. In addition, the method includes measuring the warpage of the semiconductor die on the bond-head element using a sensor, then bonding the semiconductor die to a carrier using the bond-head element.

Abstract: Integrated circuit package structures and methods of forming integrated circuit package structures are discussed. An integrated circuit package structure, in accordance with some embodiments, includes an integrated circuit package substrate with a heterogeneous bonding scheme that includes conductive pillars for bonding semiconductor devices to as well as a region including conductive connectors embedded in a dielectric for bonding additional semiconductor devices.

Abstract: Systems and methods of automatic screen mapping are presented. In one exemplary embodiment, a method is performed by a controller device that is coupled to at least one of a set of display devices that are spatially arranged so that each display device is positioned adjacent to at least one other display device and wherein each display device includes a screen structure having a set of presence sensitive sensors. Each display device is operable, for each presence sensitive sensor of the corresponding screen structure, to detect a presence signal and to radiate a presence signal. The method includes receiving an indication that a second display device of the set of display devices has detected a presence signal radiated from a presence sensitive sensor of a first display device of the set of display devices so as to determine a spatial arrangement of the first and second display devices.

Abstract: A package structure is provided. The package structure includes a substrate and a semiconductor chip over the substrate. The package structure also includes a protective frame laterally surrounding the semiconductor chip. The package structure further includes an underfill element between the semiconductor chip and the protective frame. A portion of the underfill element is directly below the protective frame.

Abstract: A method of making a semiconductor device includes manufacturing doped zones in a first semiconductor material over a substrate. The method further includes forming an isolation structure between adjacent doped zones of the first semiconductor material. The method further includes manufacturing lines extending in a first direction over the doped zones of the first semiconductor material, wherein each of the lines has a line width measured along a second direction perpendicular to the first direction. The method further includes trimming the lines into line segments having ends over the isolation structure. The method further includes etching a transistor gate electrode over the substrate, wherein transistor gate electrode has a gate electrode width measured along the second direction, and wherein the line width is substantially similar to the gate electrode width.

Abstract: A semiconductor device includes a first integrated circuit die and a second integrated circuit die. The first integrated circuit die includes a conductive paste on a first surface of the first integrated circuit die, wherein the conductive paste is in direct contact with the first surface of the first integrated circuit die. The second integrated circuit die is disposed aside the first integrated circuit die, wherein a surface of the conductive paste is substantially coplanar with a surface of the second integrated circuit die.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, an encapsulant, a protection layer and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The encapsulant is disposed over the interposer and laterally encapsulating the at least one semiconductor die. The connectors are disposed on the second surface of the interposer and electrically connected with the at least one semiconductor die through the interposer. The protection layer is disposed on the second surface of the interposer and surrounding the connectors. The sidewalls of the interposer include slanted sidewalls connected to the second surface, and the protection layer is in contact with the slant sidewalls of the interposer.

Abstract: A Projected Capacitive (PCAP) display including multiple arrays of conductive electrodes performs a dual function. In a first function, the PCAP display uses the conductive electrode arrays to generate an electrostatic field and determines the presence and position of a conductive object based on small changes it detects in the capacitance of that electrostatic field. In a second function, the PCAP display uses the same conductive electrode arrays to generate a magnetic field. As a user swipes the card across the surface of the PCAP display, it causes small changes in the generated magnetic field. The PCAP display retrieves the data magnetically encoded onto the magnetic stripe card based on the changes it detects in the magnetic field.

Abstract: A package structure includes a semiconductor die, a first insulating encapsulant, a plurality of first conductive features, an interconnect structure and bump structures. The semiconductor die includes a plurality of conductive pillars made of a first material. The first insulating encapsulant is encapsulating the semiconductor die. The first conductive features are disposed on the semiconductor die and electrically connected to the conductive pillars. The first conductive features include at least a second material different from the first material. The interconnect structure is disposed on the first conductive features, wherein the interconnect structure includes a plurality of connection structures made of the second material. The bump structures are electrically connecting the first conductive features to the connection structures, wherein the bump structures include a third material different from the first material and the second material.

Abstract: A package structure includes a circuit substrate, a semiconductor device, a plurality of cooling pins, a cooler lid, an anti-fouling coating and a top lid. The semiconductor device is disposed on and electrically connected to the circuit substrate. The cooling pins are disposed on the semiconductor device. The cooler lid is attached to the cooling pins, wherein the cooler lid includes an inlet opening and an outlet opening exposing portions of the cooling pins. The anti-fouling coating is coated on the cooling pins and on an inner surface of the cooler lid. The top lid is attached to an outer surface of the cooler lid.

Abstract: A package includes a laser diode includes a bonding layer; a first dielectric layer over the laser diode, wherein the first dielectric layer is directly bonded to the bonding layer of the laser diode; a first silicon nitride waveguide in the first dielectric layer, wherein the first silicon nitride waveguide extends over the laser diode; a second dielectric layer over the first silicon nitride waveguide; a silicon waveguide in the second dielectric layer; an interconnect structure over the silicon waveguide; and conductive features extending through the first dielectric layer and the second dielectric layer to electrically contact the interconnect structure.