Abstract: A improved termination structure for semiconductor power devices is disclosed, comprising a trenched field plate formed not only along trench sidewall but also on trench bottom of the wide termination trench by doing poly-silicon CMP so that body ion implantation is blocked by the trenched field plate on the trench bottom to prevent a body region formation underneath the trench bottom of the wide termination trench, degrading avalanche voltage.

Abstract: A power semiconductor power device having composite trench bottom oxide and multiple trench floating gates is disclosed. The gate charge is reduced by forming a pad oxide surrounding a HDP oxide on trench bottom. The multiple trenched floating gates are applied in termination for saving body mask.

Abstract: A release device for detaching a male plug of a cable line from a female receptacle includes a holding portion, an accommodating portion, a connecting portion and an engaging portion. The accommodating portion includes a first guiding part that is configured for alignment between the accommodating portion and the male plug. The holding portion connects to the connecting portion that connects to the accommodating portion. The accommodating portion connects to the engaging portion, which includes a concave area that is configured for engaging the male plug.

Abstract: A hybrid IGBT device having a VIGBT and LDMOS structures comprises at least a drain trenched contact filled with a conductive plug penetrating through an epitaxial layer, and extending into a substrate; a vertical drain region surrounding at least sidewalls of the drain trenched contact, extending from top surface of the epitaxial layer to the substrate, wherein the vertical drain region having a higher doping concentration than the epitaxial layer.

Abstract: A LCD panel including an active device array substrate, an opposite substrate, a liquid crystal layer, a conductive sealant and restraining elements is provided. The active device array substrate includes common lines, transfer pads and a dielectric layer. The dielectric layer has openings exposing the transfer pads. The opposite substrate has a common electrode. The liquid crystal layer and the conductive sealant are disposed between the active device array substrate and the opposite substrate. The conductive sealant surrounds the liquid crystal layer. The openings are corresponding to corners of the conductive sealant. The conductive sealant fills the openings and the common electrode is electrically connected to the transfer pads through the conductive sealant. Further, the restraining elements are between the active device array substrate and the opposite substrate and are distributed around the corners of the conductive sealant such that the conductive sealant is forced to fill into the openings.

Abstract: A semiconductor power device with trenched floating gates having thick bottom oxide as termination is disclosed. The gate charge is reduced by forming a HDP oxide layer padded by a thermal oxide layer on trench bottom and a top surface of mesa areas between adjacent trenched gates. Therefore, only three masks are needed to achieve the device structure.

Abstract: A trench MOSFET with split gates and diffused drift region for on-resistance reduction is disclosed. Each of the split gates is symmetrically disposed in the middle of the source electrode and adjacent trench sidewall of a deep trench. The inventive structure can save a mask for definition of the location of the split gate electrodes. Furthermore, the fabrication method can be implemented more reliably with lower cost.

Abstract: A trench MOSFET comprising a plurality of trenched gates surrounded by source regions encompassed in body regions in active area. A plurality of trenched source-body contact structure penetrating through the source regions and extending into the body regions, are filled with tungsten plugs padded with a Ti layer, a first and a second TiN layer, wherein the second TiN layer is deposited after Ti silicide formation to avoid W spiking occurrence.

Abstract: Exemplary backlight driving method and display device are provided. The display device includes a light source array. The light source array includes a first group of light-emitting rows and a second group of light-emitting rows. The backlight driving method includes the steps of: firstly, receiving a gate driving frequency of the display device; subsequently, generating a backlight driving frequency according to the gate driving frequency; and afterwards, sequentially providing a first row driving voltage to the first group of light-emitting rows in a first time period and sequentially providing a second row driving voltage to the second group of light-emitting rows in a second time period, according to the backlight driving frequency. The first time period and the second time period have different phases from each other, and the gate driving frequency is different from the backlight driving frequency.

Abstract: A miniature lens auto-focusing structure includes a housing having a top plate; a base plate connectable to the housing to define an inner space between them; a lens module wound around by a coil; and at least one spring member holding and suspending the lens module in the inner space without causing the lens module to contact with the top plate and the base plate. With these arrangements, the spring member is not in a pre-tensioning state when the miniature lens auto-focusing structure is in a non-actuated state. Therefore, the miniature lens auto-focusing structure requires less actuating current and has smaller lens tilt angle than the conventional VCM auto-focusing structure, and can be manufactured at further reduced component cost.

Abstract: A sensing device is provided to sense light and generates a sensing output signal indicating intensity of the light. The sensing device includes a photo element, a comparison circuit, and a logic circuit. The photo element senses the light and generates a current signal at a first node. The comparison circuit is coupled to the first node and receives the current signal. The comparison circuit includes a filter for filtering a high-frequency component on the current signal, and the comparison circuit generates a result signal according to the filtered current signal. The logic circuit receives the result signal and performs a logic operation to the result signal to generate the sensing output signal.

Abstract: A super-junction trench MOSFET is disclosed for high voltage device by applying a first doped column region of first conductivity type between a pair of second doped column regions of second conductivity type adjacent to sidewalls of a pair of deep trenches with buried voids in each unit cell for super-junction. Meanwhile, at least one trenched gate and multiple trenched source-body contacts are formed in each unit cell between the pair of deep trenches.

Abstract: A trench MOSFET device with embedded Schottky rectifier, Gate-Drain and Gate-Source clamp diodes on single chip is formed to achieve device shrinkage and performance improvement. The present semiconductor devices achieve low Vf and reverse leakage current for embedded Schottky rectifier, have overvoltage protection for Gate-Source clamp diode and avalanche protection for Gate-Drain clamp diode.

Abstract: A trench semiconductor power device integrated with a Gate-Source and a Gate-Drain clamp diodes without using source mask is disclosed, wherein a plurality source regions of a first conductivity type of the trench semiconductor device and multiple doped regions of the first conductivity type of the clamp diodes are formed simultaneously through contact open areas defined by a contact mask.

Abstract: A super-junction trench MOSEET is disclosed for high voltage device by applying a first doped column region of first conductivity type between a pair of second doped column regions of second conductivity type adjacent to sidewalls of a pair of deep trenches in each unit cell for super-junction. Meanwhile, at least one trenched gate and multiple trenched source-body contacts are formed in each unit cell between the pair of deep trenches.

Abstract: A semiconductor power device having shielded gate structure integrated with a trenched clamp diode formed in a semiconductor silicon layer, wherein the shielded gate structure comprises a shielded electrode formed by a first poly-silicon layer and a gate electrode formed by a second poly-silicon layer. The trenched clamp diode is formed by the first poly-silicon layer. A shielded gate mask used to define the shielded gate is also used to define the trenched clamp diode. Therefore, one poly-silicon layer and a mask for the trenched clamp diode are saved.

Abstract: A trench MOSFET comprising a plurality of transistor cells, multiple trenched floating gates in termination area is disclosed. The trenched floating gates have trench depth equal to or deeper than body junction depth of body regions in active area. In some preferred embodiments, the trench MOSFET further comprises a gate metal runner surrounding outside the source metal and extending to the gate metal pad. Furthermore, the termination area further comprises an EPR surrounding outside the trenched floating gates.

Abstract: A trench semiconductor power device having active cells under gate metal pad to increase total active area for lowering on-resistance is disclosed. The gate metal pad is not only for gate wire bonding but also for active cells disposition. Therefore, the device die can be shrunk so that the number of devices per wafer is increased for die cost reduction. Moreover, the device can be packaged into smaller type package for further cost reduction.

Abstract: A power semiconductor device with improved avalanche capability structures is disclosed. By forming at least an avalanche capability enhancement doped regions with opposite conductivity type to epitaxial layer underneath an ohmic contact doped region which surrounds at least bottom of trenched contact filled with metal plug between two adjacent gate trenches, avalanche current is enhanced with the disclosed structures.

Abstract: A trench MOSFET comprising multiple trenched floating gates in termination area is disclosed. The trenched floating gates have trench depth equal to or deeper than body junction of body regions in active area. The trench MOSFET further comprise an EPR surrounding outside the multiple trenched floating gates in the termination area.