Patents by Inventor Guobiao Zhang

Guobiao Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Simulation Processor with In-Package Look-Up Table
    Publication number: 20170323041
    Abstract: The present invention discloses a simulation processor for simulating a system comprising a system component. The simulation processor comprises a memory die and a logic die. The memory die comprises a look-up table circuit (LUT) for storing data related to a mathematical model of the system component. The logic die comprises an arithmetic logic circuit (ALC) for performing arithmetic operations on the model-related data. The memory die and the logic die are located in a same package.
    Type: Application
    Filed: May 4, 2017
    Publication date: November 9, 2017
    Applicant: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao ZHANG
  • Three-Dimensional Vertical One-Time-Programmable Memory
    Publication number: 20170301674
    Abstract: The present invention discloses a three-dimensional vertical read-only memory (3D-OTPV). It comprises a plurality of vertical OTP strings formed side-by-side on a substrate circuit. Each OTP string is vertical to the substrate and comprises a plurality of vertically stacked OTP cells. Each OTP cell comprises an antifuse layer. The antifuse layer is irreversibly switched from a high-resistance state to a low-resistance state during programming.
    Type: Application
    Filed: April 16, 2017
    Publication date: October 19, 2017
    Applicant: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao ZHANG
  • Multi-Bit-Per-Cell Three-Dimensional One-Time-Programmable Memory
    Publication number: 20170301405
    Abstract: The present invention discloses a multi-bit-per-cell three-dimensional read-only memory (3D-OTPMB). It comprises a plurality of OTP cells stacked above a semiconductor substrate. Each OTP cell comprises an antifuse layer, which is irreversibly switched from a high-resistance state to a low-resistance state during programming. By adjusting the programming current, the programmed antifuses have different resistances.
    Type: Application
    Filed: April 14, 2017
    Publication date: October 19, 2017
    Applicant: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao ZHANG
  • Night Detection of Side-by-Side Parked Vehicles
    Publication number: 20170289351
    Abstract: To detect side-by-side parked vehicles at night, the present invention discloses a night-detection device and method. The night-detection device comprises a moving-vehicle sensor and a parked-vehicle sensor. It uses the light beam from a passing-by vehicle to extract at least a reflection of at least a head-light or at least a portion of a front bumper.
    Type: Application
    Filed: June 20, 2017
    Publication date: October 5, 2017
    Applicant: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao ZHANG
  • Integrated Neuro-Processor Comprising Three-Dimensional Memory Array
    Publication number: 20170270403
    Abstract: The present invention discloses an integrated neuro-processor comprising at least a three-dimensional memory (3D-M) array. The 3D-M array stores the synaptic weights, while the neuro-processing circuit performs neural processing. The 3-D integration between the 3D-M array and the neuro-processing circuit not only improves the computational power per die area, but also greatly increases the storage capacity per die area.
    Type: Application
    Filed: March 21, 2017
    Publication date: September 21, 2017
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Configurable Gate Array Based on Three-Dimensional Writable Memory
    Publication number: 20170257101
    Abstract: The present invention discloses a configurable gate array based on three-dimensional printed memory (3D-W). It comprises an array of configurable computing elements, an array of configurable logic elements and an array of configurable interconnects. Each configurable computing element comprises at least a 3D-W array, which is electrically programmable and can be loaded with a look-up table (LUT) for a math function.
    Type: Application
    Filed: March 6, 2017
    Publication date: September 7, 2017
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Mobile Vending Machine
    Publication number: 20170255921
    Abstract: The present invention discloses a mobile vending machine and the associated card-rental method for long-distance travels. The mobile vending machine contains a large number of content cards (e.g. TF cards). A user may rent a content card from the mobile vending machine. To facilitate playback in all types of mobile devices, the present invention further discloses several preferred multi-slot content/power pack and a preferred multi-slot mobile device.
    Type: Application
    Filed: March 1, 2017
    Publication date: September 7, 2017
    Applicant: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao ZHANG
  • Field-Repair System and Method of Mask-Programmed Read-Only Memory
    Publication number: 20170255516
    Abstract: The present invention discloses field-repair system and method for a mask-programmed memory (mask-ROM). The mask-ROM data are encoded with an error-checking-and-correction (ECC) scheme. A self-checking circuit detects errors in read-out data without using any external data. When an error is detected, a communicating circuit fetches the good data from a remote server. As a result, most of the mask-ROM data can be checked and repaired in the field.
    Type: Application
    Filed: March 6, 2016
    Publication date: September 7, 2017
    Applicant: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao ZHANG
  • Distributed Pattern Processor Comprising Three-Dimensional Memory Array
    Publication number: 20170255834
    Abstract: The present invention discloses a distributed pattern processor. The distributed pattern processor not only stores patterns permanently, but also processes them using massive parallelism. It comprises a plurality of storage-processing units (SPU), with each SPU comprising a pattern-processing circuit and at least a three-dimensional memory (3D-M) array storing at least a pattern. The 3D-M array is vertically stacked above the pattern-processing circuit.
    Type: Application
    Filed: March 7, 2017
    Publication date: September 7, 2017
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Configurable Gate Array Based on Three-Dimensional Printed Memory
    Publication number: 20170257100
    Abstract: The present invention discloses a configurable gate array based on three-dimensional printed memory (3D-P). It comprises an array of configurable computing elements, an array of configurable logic elements and a plurality of configurable interconnects. Each configurable computing element can selectively realize a math function from a math library. It comprises a plurality of 3D-P arrays storing the look-up tables (LUT) for the math functions in the math library.
    Type: Application
    Filed: March 5, 2017
    Publication date: September 7, 2017
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Three-dimensional offset-printed memory with multiple bits-per-cell
    Patent number: 9741448
    Abstract: The present invention discloses a three-dimensional offset-printed memory (3D-oP) with multiple bits-per-cell. The mask-patterns for different bits-in-a-cell are merged onto a same data-mask. At different printing steps, a wafer is offset by different values with respect to the data-mask. Accordingly, data-patterns from a same data-mask are printed into different bits-in-a-cell.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: August 22, 2017
    Assignees: HangZhou HaiChun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Three-dimensional 3D-oP-based package
    Patent number: 9741697
    Abstract: The present invention discloses a three-dimensional 3D-oP (three-dimensional offset-printed memory)-based package (3D2-oP). The mask-patterns for different dice in a same 3D2-oP package are merged onto a same data-mask. At different printing steps, a wafer is offset by different values with respect to the data-mask. Accordingly, data-patterns from a same data-mask are printed into different dice in a same 3D2-oP package.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: August 22, 2017
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Processor Comprising Three-Dimensional Memory (3D-M) Array
    Publication number: 20170237440
    Abstract: The present invention discloses a processor comprising three-dimensional memory (3D-M) array (3D-processor). Instead of logic-based computation (LBC), the 3D-processor uses memory-based computation (MBC). It comprises an array of computing elements, with each computing element comprising an arithmetic logic circuit (ALC) and a 3D-M-based look-up table (3DM-LUT). The ALC performs arithmetic operations on the LUT data, while the 3DM-LUT is stored in at least one 3D-M array.
    Type: Application
    Filed: April 13, 2017
    Publication date: August 17, 2017
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventors: Guobiao ZHANG, Chen SHEN
  • Mixed Three-Dimensional Memory
    Publication number: 20170229158
    Abstract: The present invention discloses a mixed three-dimensional memory (3D-Mx). Both data and codes are stored in a same 3D-Mx die. Data, which require a lower cost per bit and can tolerate slow access, are stored in large memory arrays, whereas codes, which require fast access and can tolerate a higher cost per bit, are stored in small memory arrays.
    Type: Application
    Filed: April 23, 2017
    Publication date: August 10, 2017
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Compact Three-Dimensional Memory with an Above-Substrate Decoding Stage
    Publication number: 20170221529
    Abstract: The above-substrate decoding stage of a compact three-dimensional memory (3D-Mc) could be an intra-level decoding stage, an inter-level decoding stage, or a combination thereof. For the intra-level decoding stage, contact vias can be shared by address-lines in the same memory level; for the inter-level decoding stage, contact vias can be shared by address-lines from different memory levels.
    Type: Application
    Filed: April 19, 2017
    Publication date: August 3, 2017
    Inventor: Guobiao ZHANG
  • Compact Three-Dimensional Memory with Semi-Conductive Address Line Portion
    Publication number: 20170221528
    Abstract: In a compact three-dimensional memory (3D-MC), a memory array and an above-substrate decoding stage thereof are formed on a same memory level. For the memory devices in the memory array, the overlap portion and the non-overlap portions of the x-line are both highly-conductive; for the decoding device in the above-substrate decoding stage, while the non-overlap portions are still highly-conductive, the overlap portion is semi-conductive.
    Type: Application
    Filed: April 13, 2017
    Publication date: August 3, 2017
    Applicant: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao ZHANG
  • Manufacturing Methods of MOSFET-Type Compact Three-Dimensional Memory
    Publication number: 20170194379
    Abstract: Manufacturing methods of MOSFET-type compact three-dimensional memory (3D-MC) are disclosed. In a memory level stacked above the substrate, an x-line extends from a memory array to an above-substrate decoding stage. A MOSFET-type transistor is formed on the x-line as a decoding device for the above-substrate decoding stage, where the overlap portion of the x-line with the control-line (c-line) is semi-conductive.
    Type: Application
    Filed: March 8, 2017
    Publication date: July 6, 2017
    Applicant: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao ZHANG
  • Manufacturing Methods of JFET-Type Compact Three-Dimensional Memory
    Publication number: 20170186817
    Abstract: Manufacturing methods of JFET-type compact three-dimensional memory (3D-MC) are disclosed. In a memory level stacked above the substrate, an x-line extends from a memory array to an above-substrate decoding stage. A JFET-type transistor is formed on the x-line as a decoding device for the above-substrate decoding stage, where the overlap portion of the x-line with the control-line (c-line) is semi-conductive.
    Type: Application
    Filed: March 9, 2017
    Publication date: June 29, 2017
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Compact Three-Dimensional Mask-Programmed Read-Only Memory
    Publication number: 20170186811
    Abstract: A compact three-dimensional mask-programmed read-only memory (3D-MPROMc) is disclosed. Its memory array and a decoding stage thereof are formed on a same memory level above the substrate. The memory layers of the memory devices in the memory array have at least two different thicknesses, while the middle layer of the decoding device in the decoding stage has the same thickness as the thinnest memory layer.
    Type: Application
    Filed: March 10, 2017
    Publication date: June 29, 2017
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Night detection of parked vehicles
    Patent number: 9688197
    Abstract: To detect parked vehicles at night, the present invention discloses night-detection device and method. The night-detection device comprises a moving-vehicle sensor and a parked-vehicle sensor. It uses the light beam from a passing-by vehicle to detect parked vehicles.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: June 27, 2017
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang