Patents by Inventor Guobiao Zhang

Guobiao Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Offset-printing method for three-dimensional package
    Patent number: 9990961
    Abstract: The present invention discloses an offset-printing method for a three-dimensional 3D-oP (three-dimensional offset-printed memory)-based package. The mask-patterns for different 3D-op dice are merged onto a same data-mask. At different printing steps, a wafer is offset by different values with respect to the data-mask. Accordingly, data-patterns from a same data-mask are printed into different 3D-oP dice.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: June 5, 2018
    Assignees: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao Zhang
  • Offset-printing method for three-dimensional printed memory with multiple bits-per-cell
    Patent number: 9990960
    Abstract: The present invention discloses an offset-printing method for a three-dimensional printed memory with multiple bits-per-cell. The mask-patterns for different bits-in-a-cell are merged onto a multi-region data-mask. At different printing steps, a wafer is offset by different values with respect to the data-mask. Accordingly, data-patterns from a same data-mask are printed into different bits-in-a-cell.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: June 5, 2018
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Three-Dimensional Vertical One-Time-Programmable Memory Comprising No Separate Diode Layer
    Publication number: 20180137927
    Abstract: The present invention discloses a three-dimensional vertical read-only memory (3D-OTPV) comprising no separate diode layer. It comprises a plurality of vertical address line, a plurality of memory holes through said vertical address line, a plurality of antifuse layers and vertical address lines in said memory holes. The memory holes comprise no separate diode layer. The horizontal and vertical address lines comprise different metallic materials.
    Type: Application
    Filed: January 13, 2018
    Publication date: May 17, 2018
    Applicant: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao ZHANG
  • Offset-printing method for three-dimensional printed memory
    Patent number: 9959910
    Abstract: The present invention discloses an offset-printing method for a three-dimensional printed memory. The mask-patterns for different memory levels are merged onto a multi-region data-mask. At different printing steps, a wafer is offset by different values with respect to the data-mask. Accordingly, data-patterns from a same data-mask are printed into different memory levels.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: May 1, 2018
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Configurable gate array based on three-dimensional printed memory
    Patent number: 9948306
    Abstract: The present invention discloses a configurable gate array based on three-dimensional printed memory (3D-P). It comprises an array of configurable computing elements, an array of configurable logic elements and a plurality of configurable interconnects. Each configurable computing element can selectively realize a math function from a math library. It comprises a plurality of 3D-P arrays storing the look-up tables (LUT) for the math functions in the math library.
    Type: Grant
    Filed: March 5, 2017
    Date of Patent: April 17, 2018
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Configurable Computing Array Based on Three-Dimensional Vertical Writable Memory
    Publication number: 20180048315
    Abstract: The present invention discloses a configurable computing array. It is a monolithic integrated circuit comprising at least a configurable computing element and a configurable logic element. The configurable computing element comprises at least a three-dimensional vertical writable memory (3D-WV) array, which is stacked above the configurable logic element and stores at least a portion of a look-up table (LUT) for a math function.
    Type: Application
    Filed: October 25, 2017
    Publication date: February 15, 2018
    Applicant: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao ZHANG
  • Configurable Computing-Array Package
    Publication number: 20180048317
    Abstract: The present invention discloses a configurable computing-array package. It comprises a configurable computing die including an array of configurable computing elements and a configurable logic die including an array of configurable logic elements. Each configurable computing element comprises at least a writable-memory array, which stores at least a portion of a look-up table (LUT) for a math function.
    Type: Application
    Filed: October 25, 2017
    Publication date: February 15, 2018
    Applicant: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao ZHANG
  • Configurable Computing Array Comprising Three-Dimensional Writable Memory
    Publication number: 20180048313
    Abstract: The present invention discloses a configurable computing array comprising three-dimensional writable memory (3D-W). It is a monolithic integrated circuit comprising an array of configurable computing elements, an array of configurable logic elements and an array of configurable interconnects. Each configurable computing element comprises at least a 3D-W array, which stores at least a portion of a look-up table (LUT) for a math function.
    Type: Application
    Filed: October 25, 2017
    Publication date: February 15, 2018
    Applicant: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao ZHANG
  • Configurable Computing Array Using Two-Sided Integration
    Publication number: 20180048316
    Abstract: The present invention discloses a configurable computing array using two-sided integration. It is a monolithic integrated circuit comprising at least a configurable computing element located on one side of the substrate and at least a configurable logic element on the other side of the substrate. Each configurable computing element comprises at least a writable-memory array, which stores at least a portion of a look-up table (LUT) for a math function.
    Type: Application
    Filed: October 25, 2017
    Publication date: February 15, 2018
    Applicant: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao ZHANG
  • Configurable Computing Array
    Publication number: 20180048314
    Abstract: The present invention discloses a configurable computing array. It comprises an array of configurable computing elements and an array of configurable logic elements. Each configurable computing element comprises at least a writable-memory array, which stores at least a portion of a look-up table (LUT) for a math function.
    Type: Application
    Filed: October 25, 2017
    Publication date: February 15, 2018
    Applicant: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao ZHANG
  • Configurable Gate Array Based on Three-Dimensional Writable Memory
    Publication number: 20180041216
    Abstract: The present invention discloses a configurable gate array based on three-dimensional writable memory (3D-W). It comprises an array of configurable computing elements, an array of configurable logic elements and an array of configurable interconnects. Each configurable computing element comprises at least a 3D-W array, which is electrically programmable and can be loaded with a look-up table (LUT) for a math function.
    Type: Application
    Filed: October 13, 2017
    Publication date: February 8, 2018
    Inventor: Guobiao ZHANG
  • Processor For Enhancing Network Security
    Publication number: 20180034831
    Abstract: The present invention discloses a processor for enhancing network security, i.e. a three-dimensional (3-D) security processor. It is a monolithic integrated circuit comprising a plurality of storage-processing units (SPU). Each SPU comprises at least a three-dimensional memory (3D-M) array for permanently storing rule/virus patterns and a pattern-processing circuit for performing pattern processing on an incoming network packet against said rule/virus patterns. The 3D-M array is stacked above the pattern-processing circuit.
    Type: Application
    Filed: October 10, 2017
    Publication date: February 1, 2018
    Applicant: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao ZHANG
  • Processor For Enhancing Computer Security
    Publication number: 20180032729
    Abstract: The present invention discloses a processor for enhancing computer security, i.e. a three-dimensional (3-D) security processor. It is a monolithic integrated circuit comprising a plurality of storage-processing units (SPU). Each SPU comprises at least a three-dimensional memory (3D-M) array for permanently storing virus patterns and a pattern-processing circuit for performing pattern processing on a scanned computer data against said virus patterns. The 3D-M array is stacked above the pattern-processing circuit.
    Type: Application
    Filed: October 10, 2017
    Publication date: February 1, 2018
    Applicant: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao ZHANG
  • Configurable gate array based on three-dimensional writable memory
    Patent number: 9838021
    Abstract: The present invention discloses a configurable gate array based on three-dimensional writable memory (3D-W). It comprises an array of configurable computing elements, an array of configurable logic elements and an array of configurable interconnects. Each configurable computing element comprises at least a 3D-W array, which is electrically programmable and can be loaded with a look-up table (LUT) for a math function.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: December 5, 2017
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Processor for Realizing at least Two Categories of Functions
    Publication number: 20170329548
    Abstract: The present invention discloses a first preferred processor comprising a fixed look-up table circuit (LTC) and a writable LTC. The fixed LTC realizes at least a common function while the writable LTC realizes at least a non-common function. The present invention further discloses a second preferred processor comprising a two-dimensional (2-D) LTC and a three-dimensional (3-D) LTC. The 2-D LTC realizes at least a fast function while the 3-D LTC realizes at least a non-fast function.
    Type: Application
    Filed: May 10, 2017
    Publication date: November 16, 2017
    Applicant: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao ZHANG
  • Configurable Processor with Backside Look-Up Table
    Publication number: 20170322774
    Abstract: The present invention discloses a configurable processor with a backside look-up table. The configurable processor comprises a look-up table circuit (LUT) on the backside of the processor substrate and an arithmetic logic circuit (ALC) on the front side of the processor substrate. The LUT stores data related to a desired function. The ALC performs arithmetic operations on the data read out from the LUT.
    Type: Application
    Filed: May 6, 2017
    Publication date: November 9, 2017
    Applicant: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao ZHANG
  • Simulation Processor with Backside Look-Up Table
    Publication number: 20170323042
    Abstract: The present invention discloses a simulation processor for simulating a system comprising a system component. The simulation processor comprises a look-up table circuit (LUT) and an arithmetic logic circuit (ALC). The LUT is formed on the backside of the processor substrate and stores data related to a mathematical model of the system component. The ALC is formed on the front side of the processor substrate and performs arithmetic operations on the model-related data. The LUT and the ALC are communicatively coupled by a plurality of through-silicon vias (TSV).
    Type: Application
    Filed: May 4, 2017
    Publication date: November 9, 2017
    Applicant: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao ZHANG
  • Processor with In-Package Look-Up Table
    Publication number: 20170322906
    Abstract: The present invention discloses a processor for computing a mathematical function. The processor comprises a memory die and a logic die. The memory die comprises a look-up table circuit (LUT) for storing data related to the mathematical function. The logic die comprises an arithmetic logic circuit (ALC) for performing arithmetic operations on the function-related data. The memory die and the logic die are located in a same package.
    Type: Application
    Filed: May 4, 2017
    Publication date: November 9, 2017
    Applicant: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao ZHANG
  • Configurable Processor with In-Package Look-Up Table
    Publication number: 20170322771
    Abstract: The present invention discloses a configurable processor with an in-package look-up table. The configurable processor comprises a programmable memory die and a logic die located in a same package. The programmable memory die comprises a look-up table circuit (LUT) for storing data related to a desired function. The logic die comprises an arithmetic logic circuit (ALC) for performing arithmetic operations on the data read out from the LUT.
    Type: Application
    Filed: May 6, 2017
    Publication date: November 9, 2017
    Applicant: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao ZHANG
  • Processor with Backside Look-Up Table
    Publication number: 20170322770
    Abstract: The present invention discloses a processor for computing a mathematical function. The processor comprises a look-up table circuit (LUT) and an arithmetic logic circuit (ALC). The LUT is formed on the backside of the processor substrate and stores data related to the mathematical function. The ALC is formed on the front side of the processor substrate and performs arithmetic operations on the function-related data. The LUT and the ALC are communicatively coupled by a plurality of through-silicon vias (TSV).
    Type: Application
    Filed: May 4, 2017
    Publication date: November 9, 2017
    Applicant: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao ZHANG