Patents by Inventor Gurtej Sandhu

Gurtej Sandhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160103283
    Abstract: Devices and systems to perform optical alignment by using one or more liquid crystal layers to actively steer a light beam from an optical fiber to an optical waveguide integrated on a chip. An on-chip feedback mechanism can steer the beam between the fiber and a grating based waveguide to minimize the insertion loss of the system.
    Type: Application
    Filed: December 17, 2015
    Publication date: April 14, 2016
    Inventors: Roy Meade, Gurtej Sandhu
  • Patent number: 9310552
    Abstract: Described embodiments include photonic integrated circuits and systems with photonic devices, including thermal isolation regions for the photonic devices. Methods of fabricating such circuits and systems are also described.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: April 12, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Roy Meade, Gurtej Sandhu
  • Patent number: 9305826
    Abstract: A method of forming a substrate with isolation areas suitable for integration of electronic and photonic devices is provided. A common reticle and photolithographic technique is used to fabricate a mask defining openings for etching first and second trench isolation areas in a substrate, with the openings for the second trench isolation areas being wider than the openings for the first trench isolation areas. The first and second trench isolation areas are etched in the substrate through the mask. The second trench isolation areas are further etched to the deeper than the first trench isolation areas. The trench isolation areas are filled with oxide material. Electrical devices can be formed on the substrate and electrically isolated by the first trench isolation areas and photonic devices can be formed over the second trench isolation areas and be optically isolated from the substrate.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: April 5, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Roy Meade, Gurtej Sandhu
  • Publication number: 20160078912
    Abstract: A magnetic memory cell including a piezoelectric material, and methods of operating the memory cell are provided. The memory cell includes a stack, and the piezoelectric material may be formed as a layer in the stack or adjacent the layers of the cell stack. The piezoelectric material may be used to induce a transient stress during programming of the memory cell to reduce the critical switching current of the memory cell.
    Type: Application
    Filed: November 20, 2015
    Publication date: March 17, 2016
    Inventors: Jun Liu, Steve Kramer, Gurtej Sandhu
  • Patent number: 9274272
    Abstract: A photonic device and methods of formation that provide an area providing reduced optical coupling between a substrate and an inner core of the photonic device are described. The area is formed using holes in the inner core and an outer cladding. The holes may be filled with materials which provide a photonic crystal. Thus, the photonic device may function as a waveguide and as a photonic crystal.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: March 1, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej Sandhu, Roy Meade
  • Patent number: 9235097
    Abstract: Devices and systems to perform optical alignment by using one or more liquid crystal layers to actively steer a light beam from an optical fiber to an optical waveguide integrated on a chip. An on-chip feedback mechanism can steer the beam between the fiber and a grating based waveguide to minimize the insertion loss of the system.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: January 12, 2016
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Roy Meade, Gurtej Sandhu
  • Patent number: 9224458
    Abstract: A memory array is disclosed having bipolar current-voltage (IV) resistive random access memory cells with built-in “on” state rectifying IV characteristics. In one embodiment, a bipolar switching resistive random access memory cell may have a metal/solid electrolyte/semiconductor stack that forms a Schottky diode when switched to the “on” state. In another embodiment, a bipolar switching resistive random access memory cell may have a metal/solid electrolyte/tunnel barrier/electrode stack that forms a metal-insulator-metal device when switched to the “on” state. Methods of operating the memory array are also disclosed.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: December 29, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Gurtej Sandhu
  • Patent number: 9224742
    Abstract: An integrated circuit and a method of formation provide a contact area formed at an angled end of at least one linearly extending conductive line. In an embodiment, conductive lines with contact landing pads are formed by patterning lines in a mask material, cutting at least one of the material lines to form an angle relative to the extending direction of the material lines, forming extensions from the angled end faces of the mask material, and patterning an underlying conductor by etching using said material lines and extension as a mask. In another embodiment, at least one conductive line is cut at an angle relative to the extending direction of the conductive line to produce an angled end face, and an electrical contact landing pad is formed in contact with the angled end face.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: December 29, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej Sandhu, Scott Sills
  • Patent number: 9218863
    Abstract: A magnetic memory cell including a piezoelectric material, and methods of operating the memory cell are provided. The memory cell includes a stack, and the piezoelectric material may be formed as a layer in the stack or adjacent the layers of the cell stack. The piezoelectric material may be used to induce a transient stress during programming of the memory cell to reduce the critical switching current of the memory cell.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: December 22, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Steve Kramer, Gurtej Sandhu
  • Patent number: 9209904
    Abstract: A method of operating an optical waveguide for transmitting an optical signal input to the optical waveguide with a first frequency. The optical waveguide includes a plurality of modulator circuits configured along an optical transmission channel. Each modulator circuit includes at least one resonant structure that resonates at the first frequency when the modulator circuit that includes the at least one resonant structure is at a resonant temperature. Each modulator circuit has a different resonant temperature.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: December 8, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Roy Meade, Gurtej Sandhu
  • Patent number: 9196753
    Abstract: Methods, devices, and systems are provided for a select device that can include a semiconductive stack of at least one semiconductive material formed on a first electrode, where the semiconductive stack can have a thickness of about 700 angstroms (?) or less. Each of the at least one semiconductive material can have an associated band gap of about 4 electron volts (eV) or less and a second electrode can be formed on the semiconductive stack.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: November 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: D. V. Nirmal Ramaswamy, Gurtej Sandhu
  • Publication number: 20150301283
    Abstract: A method and apparatus are described which provide for wavelength drift compensation in a photonic waveguide by application of an electric field to a waveguide having a strained waveguide core.
    Type: Application
    Filed: April 16, 2014
    Publication date: October 22, 2015
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Lei Bi, Roy Meade, Gurtej Sandhu
  • Publication number: 20150287909
    Abstract: Techniques for reducing damage in memory cells are provided. Memory cell structures are typically formed using dry etch and/or planarization processes which damage certain regions of the memory cell structure. In one or more embodiments, certain regions of the cell structure may be sensitive to damage. For example, the free magnetic region in magnetic memory cell structures may be susceptible to demagnetization. Such regions may be substantially confined by barrier materials during the formation of the memory cell structure, such that the edges of such regions are protected from damaging processes. Furthermore, in some embodiments, a memory cell structure is formed and confined within a recess in dielectric material.
    Type: Application
    Filed: June 22, 2015
    Publication date: October 8, 2015
    Inventors: Jun Liu, Gurtej Sandhu
  • Patent number: 9120091
    Abstract: Embodiments of the present invention are generally directed to a method for disposing nanoparticles on a substrate. In one embodiment, a substrate having a plurality of recesses is provided. In this embodiment, a plurality of nanoparticles is also provided. The nanoparticles include a catalyst material coupled to one or more ligands, and these nanoparticles are disposed within respective recesses of the substrate. In some embodiments, the substrate is processed to form nanostructures, such as nanotubes or nanowires, within the recesses. Devices and systems having such nanostructures are also disclosed.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: September 1, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej Sandhu
  • Publication number: 20150243546
    Abstract: A method of forming a substrate with isolation areas suitable for integration of electronic and photonic devices is provided. A common reticle and photolithographic technique is used to fabricate a mask defining openings for etching first and second trench isolation areas in a substrate, with the openings for the second trench isolation areas being wider than the openings for the first trench isolation areas. The first and second trench isolation areas are etched in the substrate through the mask. The second trench isolation areas are further etched to the deeper than the first trench isolation areas. The trench isolation areas are filled with oxide material. Electrical devices can be formed on the substrate and electrically isolated by the first trench isolation areas and photonic devices can be formed over the second trench isolation areas and be optically isolated from the substrate.
    Type: Application
    Filed: April 28, 2015
    Publication date: August 27, 2015
    Inventors: Roy Meade, Gurtej Sandhu
  • Patent number: 9117766
    Abstract: Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed mandrels is removed and alternating layers, formed of two mutually selectively etchable materials, are deposited around the remaining spacers. Layers formed of one of the materials are then etched, leaving behind vertically-extending layers formed of the other of the materials, which form a mask pattern. Alternatively, instead of depositing alternating layers, amorphous carbon is deposited around the remaining spacers followed by a plurality of cycles of forming pairs of spacers on the amorphous carbon, removing one of the pairs of spacers and depositing an amorphous carbon layer. The cycles can be repeated to form the desired pattern. Because the critical dimensions of some features in the pattern can be set by controlling the width of the spaces between spacers, exceptionally small mask features can be formed.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: August 25, 2015
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Sanket Sant, Gurtej Sandhu, Neal R. Rueger
  • Patent number: 9099402
    Abstract: Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: August 4, 2015
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Mirzafer Abatchev, Gurtej Sandhu
  • Publication number: 20150198775
    Abstract: The disclosed embodiments relate to an integrated circuit structure and methods of forming them in which photonic devices are formed on the back end of fabricating a CMOS semiconductor structure containing electronic devices. Doped regions associated with the photonic devices are formed using microwave annealing for dopant activation.
    Type: Application
    Filed: August 31, 2012
    Publication date: July 16, 2015
    Inventor: Gurtej Sandhu
  • Patent number: 9082956
    Abstract: Techniques for reducing damage in memory cells are provided. Memory cell structures are typically formed using dry etch and/or planarization processes which damage certain regions of the memory cell structure. In one or more embodiments, certain regions of the cell structure may be sensitive to damage. For example, the free magnetic region in magnetic memory cell structures may be susceptible to demagnetization. Such regions may be substantially confined by barrier materials during the formation of the memory cell structure, such that the edges of such regions are protected from damaging processes. Furthermore, in some embodiments, a memory cell structure is formed and confined within a recess in dielectric material.
    Type: Grant
    Filed: April 4, 2011
    Date of Patent: July 14, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Gurtej Sandhu
  • Publication number: 20150192737
    Abstract: Disclosed method and apparatus embodiments provide a photonic device with optical isolation from a supporting substrate. A generally rectangular cavity in cross section is provided below an element of the photonic device and the element may be formed from a ledge of the supporting substrate which is over the cavity.
    Type: Application
    Filed: March 19, 2015
    Publication date: July 9, 2015
    Inventors: Gurtej Sandhu, Roy Meade