Patents by Inventor Hans Hsu

Hans Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10991665
    Abstract: A semiconductor package and a packaged electronic device are described. The semiconductor package has a foundation layer and a planar filtering circuit. The circuit is formed in the foundation layer to provide EMI/RFI mitigation. The circuit has one or more conductive traces that are patterned to form an equivalent circuit of inductors and capacitors. The one or more conductive traces include planar metal shapes, such as meanders, loops, inter-digital fingers, and patterned shapes, to reduce the z-height of the package. The packaged electronic device has a semiconductor die, a foundation layer, a motherboard, a package, and the circuit. The circuit removes undesirable interferences generated from the semiconductor die. The circuit has a z-height that is less than a z-height of solder balls used to attach the foundation layer to the motherboard. A method of forming a planar filtering circuit in a foundation layer is also described.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: April 27, 2021
    Assignee: Intel Corporation
    Inventors: Hao-Han Hsu, Dong-Ho Han, Steven C. Wachtman, Ryan K. Kuhlmann
  • Patent number: 10971677
    Abstract: An electrically controlled nanomagnet and a spin orbit torque magnetic random access memory (SOT-MRAM) including the same are provided. The electrically controlled nanomagnet includes: a first spin-Hall material layer including a first spin-Hall material; a second spin-Hall material layer including a second spin-Hall material; and a first magnetic layer disposed between the first spin-Hall material layer and the second spin-Hall material layer, wherein the first spin-Hall material and the second spin-Hall material are substantially mirror image to each other.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: April 6, 2021
    Assignee: ACADEMIA SINICA
    Inventors: Hsin Lin, Shih-Yu Wu, Chuang-Han Hsu
  • Patent number: 10971425
    Abstract: A semiconductor device including a circuit substrate, a chip package, and a stiffener ring is provided. The chip package is disposed on and electrically connected to the circuit substrate, the chip package includes a pair of first parallel sides and a pair of second parallel sides shorter than the pair of first parallel sides. The stiffener ring is disposed on the circuit substrate, the stiffener ring includes first stiffener portions extending along a direction substantially parallel with the pair of first parallel sides and second stiffener portions extending along the direction substantially parallel with the pair of second parallel sides. The first stiffener portions are connected to the second stiffener portions, and the second stiffener portions is mechanically weaker than the first stiffener portions. A semiconductor device including stiffener lids is also provided.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Chia Chiu, Li-Han Hsu
  • Publication number: 20210098391
    Abstract: A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.
    Type: Application
    Filed: June 5, 2020
    Publication date: April 1, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Cheng Wu, Chien-Chia Chiu, Cheng-Hsien Hsieh, Li-Han Hsu, Meng-Tsan Lee, Tsung-Shu Lin
  • Patent number: 10950555
    Abstract: Semiconductor packages and a method of forming a semiconductor package are described. The semiconductor package has a foundation layer, a conductive layer formed in the foundation layer, and a magnetic layer formed between the conductive and the foundation layer. The conductive layer and the magnetic layer are coupled to form a low-profile inductor shield. The semiconductor package also has a dielectric layer formed between the magnetic and foundation layer. The foundation layer is mounted between a motherboard and a semiconductor die, where the foundation layer is attached to the motherboard with solder balls. Accordingly, the low-profile inductor shield may include a z-height that is less than a z-height of the solder balls. The low-profile inductor shield may have solder pads that are coupled to the conductive layer. The foundation layer may include at least one of voltage regulator and inductor, where the inductor is located above the low-profile inductor shield.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: March 16, 2021
    Assignee: Intel Corporation
    Inventors: Kaladhar Radhakrishnan, Jaejin Lee, Hao-Han Hsu, Chung-Hao J. Chen, Dong-Ho Han
  • Patent number: 10950577
    Abstract: An embodiment package includes a first integrated circuit die, an encapsulent around the first integrated circuit die, and a conductive line electrically connecting a first conductive via to a second conductive via. The conductive line includes a first segment over the first integrated circuit die and having a first lengthwise dimension extending in a first direction and a second segment having a second lengthwise dimension extending in a second direction different than the first direction. The second segment extends over a boundary between the first integrated circuit die and the encapsulant.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
  • Patent number: 10948811
    Abstract: An illumination system configured to provide an illumination beam and including an excitation light source and a wavelength conversion module is provided. The excitation light source is configured to emit an excited beam. The wavelength conversion module is located on a transmission path of the excited beam, and has an annular wavelength conversion region. A first part of the excited beam is incident to the annular wavelength conversion region and converted into a first color light, and a second part of the excited beam is incident to the wavelength conversion module to form a second color light. A proportional value range of the second part of the excited beam and the excited beam ranges between 5% and 30%. Moreover, a projection apparatus is also provided. The illumination system of the invention has a simple structure and a concise optical path layout.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: March 16, 2021
    Assignee: Coretronic Corporation
    Inventors: Haw-Woei Pan, Jo-Han Hsu, Chi-Tang Hsieh
  • Publication number: 20210066803
    Abstract: Described herein are techniques related one or more systems, apparatuses, methods, etc. for integrating a near field communications (NFC) coil antenna in a portable device. For example, the NFC antenna is integrated under a metal chassis of the portable device. The metal chassis and a conductive coating—that is integrated underneath the full metal chassis—are designed to include one or more slots to provide high impedance to Eddy current induced in the conductive coating.
    Type: Application
    Filed: August 14, 2020
    Publication date: March 4, 2021
    Inventors: Songnan Yang, Hao-Han Hsu, Ulun Karacaoglu, Anand Konanur, Wei Hong
  • Patent number: 10939551
    Abstract: A package includes a conductive pad, with a plurality of openings penetrating through the conductive pad. A dielectric layer encircles the conductive pad. The dielectric layer has portions filling the plurality of openings. An Under-Bump Metallurgy (UBM) includes a via portion extending into the dielectric layer to contact the conductive pad. A solder region is overlying and contacting the UBM. An integrated passive device is bonded to the UBM through the solder region.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: March 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Hsieh, Chi-Hsi Wu, Chen-Hua Yu, Der-Chyang Yeh, Hsien-Wei Chen, Li-Han Hsu, Wei-Cheng Wu
  • Publication number: 20210037222
    Abstract: An illumination system includes an excitation light source module, a light splitting and combining module, a filter module, and a wavelength conversion module. The excitation light source module provides an excitation beam. The light splitting and combining module is disposed on a transmission path of the excitation beam. The excitation beam includes a first and a second excitation beam which are different from each other in polarization state or wavelength range. The filter module is disposed on the transmission path of the excitation beam. The filter module includes a light passing area configured to allow the excitation beam to pass there-through and a light filtering area. The wavelength conversion module is disposed on the transmission path of the excitation beam reflected by the light filtering area and configured to convert the reflected excitation beam into a conversion beam. A projection apparatus including the above illumination system is also provided.
    Type: Application
    Filed: July 23, 2020
    Publication date: February 4, 2021
    Applicant: Coretronic Corporation
    Inventors: Kuan-Ta Huang, Jo-Han Hsu, Chi-Tang Hsieh, Yu-Hua Hsieh
  • Patent number: 10877646
    Abstract: An electronic device includes a display, a timer and computing hardware configured to execute a software product. Execution of the software product results in generating and rendering a graphical user interface on the display with four or more user-selectable graphical objects. Selection of a first user-selectable graphical object at a first spatial position on the graphical user interface and a movement of the selected first user-selectable graphical object along a path towards a second user-selectable graphical object at a second spatial position is detected and a position of the first user-selectable graphical object is exchanged with the position of the second user-selectable graphical object. If, during a predetermined time period, a selection of a third user-selectable graphical object and a movement of the third user-selectable graphical object towards a fourth user-selectable graphical object is detected, the positions of the third and fourth objects is exchanged.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: December 29, 2020
    Assignee: Supercell Oy
    Inventors: Mikko Kodisoja, Antti Mattila, Riku Rikala, Chih-Han Hsu, Drussila Hollanda, Patrick Corander
  • Patent number: 10867900
    Abstract: A structure includes a metal pad, a passivation layer having a portion covering edge portions of the metal pad, and a dummy metal plate over the passivation layer. The dummy metal plate has a plurality of through-openings therein. The dummy metal plate has a zigzagged edge. A dielectric layer has a first portion overlying the dummy metal plate, second portions filling the first plurality of through-openings, and a third portion contacting the first zigzagged edge.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Hsieh, Hsien-Wei Chen, Chi-Hsi Wu, Chen-Hua Yu, Der-Chyang Yeh, Li-Han Hsu, Wei-Cheng Wu
  • Patent number: 10834127
    Abstract: An email attempting to perpetrate a business email compromise (BEC) attack is detected based on similarity of the email to a known BEC email and on similarity of the email to a user email that would have been sent by the purported sender of the email. Metadata of the email is extracted and input to a BEC machine learning model to find the known BEC email among BEC email samples. The extracted metadata are also input to a personal user machine learning model of the purported sender to generate the user email.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: November 10, 2020
    Assignee: Trend Micro Incorporated
    Inventors: Che-Fu Yeh, I-Ting Lien, Ming-Lun Li, Shih-Yu Chou, Po-Yuan Teng, Yuan Jiun Tsui, Cheng-Hsin Hsu, Wen-Kwang Tsao, Shih-Han Hsu, Pei-Yin Wu, Jonathan James Oliver
  • Publication number: 20200343193
    Abstract: An embodiment is a structure including a first die having an active surface with a first center point, a molding compound at least laterally encapsulating the first die, and a first redistribution layer (RDL) including metallization patterns extending over the first die and the molding compound. A first portion of the metallization patterns of the first RDL extending over a first portion of a boundary of the first die to the molding compound, the first portion of the metallization patterns not extending parallel to a first line, the first line extending from the first center point of the first die to the first portion of the boundary of the first die.
    Type: Application
    Filed: July 13, 2020
    Publication date: October 29, 2020
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu, Tsung-Shu Lin
  • Publication number: 20200319405
    Abstract: A method for forming an embedded mirror structure is disclosed. The method includes preparing a structure that has a substrate and a waveguide layer on the substrate. The waveguide layer includes a core. Also, the waveguide has a top surface and a cavity side surface that defines a cavity opened at the top surface and aligned to the core. The method further includes coating metal particles on the cavity side surface inside the cavity of the waveguide layer to form a metal particle film on the cavity side surface.
    Type: Application
    Filed: April 3, 2019
    Publication date: October 8, 2020
    Inventors: Hsiang Han Hsu, Masao Tokunari, Koji Masuda
  • Patent number: 10788741
    Abstract: A projection device includes an illumination system, a light valve, and a projection lens. The illumination system includes an excitation light source, a wavelength conversion element, a light converging lens, and a light integration rod. The excitation light source provides an excitation beam. The wavelength conversion element converts the excitation beam into a conversion beam. A greatest width in a light spot formed on the wavelength conversion element by the excitation beam is a first distance. A greatest width in a light spot formed on the wavelength conversion element by the conversion beam is a second distance. The second distance is greater than the first distance. The light integration rod receives the conversion beam from the light converging lens. The conversion beam generated by the wavelength conversion element of the invention is effectively projected to the light integration rod.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: September 29, 2020
    Assignee: Coretronic Corporation
    Inventors: Chih-Hsien Tsai, Yao-Shun Lin, Jo-Han Hsu
  • Patent number: 10782600
    Abstract: A light source module includes a plurality of light combining elements, a plurality of first light emitting elements, and a plurality of second light emitting elements. Each of the light combining elements has a first reflecting surface and a second reflecting surface. Each of the first light emitting elements emits a first illuminating beam, and one of the first reflecting surfaces reflects the first illuminating beam to be transmitted along a light combining direction. Orthographic projections of the light combining elements on a reference plane are connected in sequence, and the reference plane is perpendicular to the light combining direction. Each of the second light emitting elements emits a second illuminating beam, and one of the second reflecting surfaces reflects the second illuminating beam to be transmitted along the light combining direction. In addition, a projector having the light source module is also provided.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: September 22, 2020
    Assignee: Coretronic Corporation
    Inventors: Haw-Woei Pan, Yao-Shun Lin, Jo-Han Hsu, Chi-Tang Hsieh
  • Patent number: 10775689
    Abstract: An illumination system includes at least one excitation light source, a holographic optical element and a phosphor wheel. The excitation light source provides a first color beam. The holographic optical element is located on a path of the first color beam and transmits the first color beam to the phosphor wheel along a first path. The phosphor wheel has a light wavelength conversion portion and a reflective portion. The light wavelength conversion portion converts the first color beam into a second color beam and reflects the second color beam back to the holographic optical element. The reflective portion reflects the first color beam back to the holographic optical element. The holographic optical element transmits the second color beam and the first color beam reflected from the phosphor wheel along a second path, and the first path is different from the second path. A projection apparatus is also provided.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: September 15, 2020
    Assignee: Coretronic Corporation
    Inventors: Haw-Woei Pan, Chi-Tang Hsieh, Chih-Hsien Tsai, Jo-Han Hsu
  • Patent number: 10775573
    Abstract: A method for forming an embedded mirror structure is disclosed. The method includes preparing a structure that has a substrate and a waveguide layer on the substrate. The waveguide layer includes a core. Also, the waveguide has a top surface and a cavity side surface that defines a cavity opened at the top surface and aligned to the core. The method further includes coating metal particles on the cavity side surface inside the cavity of the waveguide layer to form a metal particle film on the cavity side surface.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: September 15, 2020
    Assignee: International Business Machines Corporation
    Inventors: Hsiang Han Hsu, Masao Tokunari, Koji Masuda
  • Publication number: 20200281352
    Abstract: A rack assembly has two support frames and at least one shelf that are secured to the support frames by connecting assemblies. Each connecting assembly comprises a well secured to a medial surface of each vertical tube of the support frame, and a hook that extends from each end of each shelf, with each hook having an opening extending therethrough. The connecting assembly also includes a connector that is seated inside each well, each connector having a top plate that has an elongated opening, the connector also having a body that is sized and configured to fit inside a well, the body defining two wings with a space between the wings, and wherein each wing has a bump positioned in the center of the inner surface of each wing that faces the space. Each hook is inserted through the elongated opening of a corresponding connector with the bump on each wing fitted inside the opening of the hook to retain the hook inside the body of the connector.
    Type: Application
    Filed: May 27, 2020
    Publication date: September 10, 2020
    Applicant: Seville Classics Inc.
    Inventor: Li-Han Hsu