Patents by Inventor Hao Ho

Hao Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220013520
    Abstract: A high-voltage semiconductor device includes a substrate, a body region, a well region, a bulk region, a source, a drain, an isolation region, a gate structure, and a resistor. The body region and the well region are disposed in the substrate. The bulk region and the source are disposed in the body region. The drain is disposed in the well region. The isolation region is disposed on the well region. The isolation region is disposed between the drain and the source. The gate structure is disposed on the substrate. The gate structure extends onto a portion of the isolation region. The resistor is disposed on the isolation region. The resistor is electrically connected to the bulk region and the drain, or the resistor is electrically connected to the drain and/or the source.
    Type: Application
    Filed: July 10, 2020
    Publication date: January 13, 2022
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Yu-Hao HO, Hsiao-Ling CHIANG, Yueh-Chu CHIANG, Yi-Hsiang HUANG
  • Publication number: 20210311095
    Abstract: A probe card and a probe module thereof are provided. The probe card includes a first strengthening board, a fixed frame, a probe module, and a slidable frame. The first strengthening board includes a top surface, a bottom surface, and a mounting hole. An inner wall of the mounting hole is formed with an inner flange. The fixed frame is disposed on the top surface of the first strengthening board and surrounds the mounting hole. The probe module is disposed in the mounting hole and includes an outer flange including a physical region and multiple gap regions. The physical region abuts against the inner flange of the first strengthening board. The slidable frame is disposed on an inner wall of the fixed frame and is slidable between a released position and a fixed position. Multiple pressing portions are disposed on an inner wall of the slidable frame.
    Type: Application
    Filed: April 2, 2021
    Publication date: October 7, 2021
    Applicant: MPI Corporation
    Inventors: Chung-Yen Huang, Chih-Wei Wen, Sheng-Feng Xu, Fuh-Chyun Tang, Chih-Hao Ho
  • Publication number: 20210303671
    Abstract: A combination lock system includes a mobile communication device (10, 10?), a cloud server (20) and a combination lock (30, 30?). When the cloud server (20) determines that the mobile communication device (10, 10?) matches authentication information, the cloud server (20) outputs password information (22) corresponding to the authentication information to the mobile communication device (10, 10?), and the combination lock (30, 30?) obtains an electric energy and the password information (22) from the mobile communication device (10, 10?). When the combination lock (30, 30?) determines that one of the characters of the password setting module (31, 31?) matches one of the characters of the password information (22) corresponding to a corresponding arrangement order, the mobile communication device (10, 10?) displays display information.
    Type: Application
    Filed: March 24, 2020
    Publication date: September 30, 2021
    Inventor: Hsi-Hao HO
  • Publication number: 20210209921
    Abstract: A fall detection system includes first sensing devices, second sensing devices, positioning modules, a data server and a display device. The first sensing device is configured to detect a posture of a body part of a user for obtaining body part posture data. The positioning modules are configured to detect positions of the first and second sensing devices, so as to obtain corresponding body part position data. Each of the second sensing devices is disposed on a shoe to detect a posture of a user's feet and to measure a distance from an ambient object for obtaining feet posture data and distance measurement data. The data server is configured to receive the body part posture data, the body part position data, the feet posture data and the distance measurement data to determine if the user falls down.
    Type: Application
    Filed: January 6, 2021
    Publication date: July 8, 2021
    Inventors: Chih-Lung LIN, Wen-Ching CHIU, Yuan-Hao HO
  • Patent number: 10972889
    Abstract: A dual-system lock includes a lockset including a combination lock and a near field communication. The combination lock includes a contact. The near field communication includes a contacting pin. A mobile apparatus transmits a signal to the near field communication. The near field communication determines and verifies whether a verification code of the mobile apparatus is correct or not. If the near field communication determines that the verification code of the mobile apparatus is correct, the contacting pin of the near field communication is connected and contacted to the contact of the combination lock, and the near field communication transmits a message including a number to the mobile apparatus, wherein the number is a correct unlocking number. If the near field communication determines that the verification code of the mobile apparatus is incorrect, the near field communication does not transmit the message to the mobile apparatus.
    Type: Grant
    Filed: October 13, 2019
    Date of Patent: April 6, 2021
    Assignee: REAL LOCKS & SECURITY CO., LTD.
    Inventor: Hsi-Hao Ho
  • Patent number: 10921981
    Abstract: An electronic device includes a keyboard module, a silicone film, a light-emitting module, and a touch module. The keyboard module has a plurality of buttons and a point stick. The silicone film has a virtual touch region. The light-emitting module is configured below the silicone film and corresponds to the virtual touch region. The light-emitting module includes a first light-emitting unit and a second light-emitting unit. The touch module is configured below the silicone film and corresponds to the virtual touch region. The touch module includes a control chip and a sensing layer. The point stick, the first light-emitting unit, the second light-emitting unit, and the sensing layer are electrically connected to the control chip, respectively.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: February 16, 2021
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Meng-Huan Tsai, Yen-Hua Hsiao, Yun-Tung Pai, Chih-Yuan Lee, Chien-Hao Ho, Chia-Hua Wu, Kung-Ju Chen, Chia-Chi Lin, Chia-Chi Sun
  • Patent number: 10823736
    Abstract: A method, system and computer-readable medium for assessing a disease condition of a cancer of a subject, including: receiving a blood sample from the subject; isolating a plurality of circulating tumor cells (CTCs) from the blood sample; measuring at least one of cell or cell nucleus sizes of each of the plurality of CTCs; determining a measured CTC size distribution of the plurality of CTCs based on the measuring; comparing the measured CTC size distribution to a reference CTC size distribution using a computer; and assigning the disease condition of the cancer of the subject based on the comparing.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: November 3, 2020
    Assignees: The Regents of the University of California, Cedars-Sinai Medical Center
    Inventors: Hsian-Rong Tseng, Jiaoti Huang, Edwin M. Posadas, Jiefu Chen, Hao Ho, Zunfu Ke, Ker-Chau Li, Yi-Tsung Lu, Jake Lichterman, Min Song, Leland W. K. Chung
  • Patent number: 10790365
    Abstract: An LDMOS includes a body region disposed in the substrate and having a first conductivity type; a drift region disposed in the substrate and having a second conductivity type; a source region disposed in the body region and having the second conductivity type; a drain region disposed in the drift region and having the second conductivity type; an isolation region disposed in the drift region between the source region and the drain region; a gate disposed on the body region and the drift region; a source field plate electrically connected to the source region; a drain field plate electrically connected to the drain region; and a first gate plate electrically connected to the gate. The first gate plate is correspondingly disposed above the gate. The shapes of the first gate plate and the gate are substantially the same when viewed from a top view.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: September 29, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Wen-Hsin Lin, Yu-Hao Ho, Shin-Cheng Lin, Cheng-Tsung Wu
  • Patent number: 10692786
    Abstract: A semiconductor structure includes a substrate, a first insulating layer, a second insulating layer, a first seal ring structure, a second seal ring structure, and a passivation layer. The substrate has a chip region and a seal ring region. The first insulating layer is on the substrate. The second insulating layer is on the first insulating layer. The first seal ring structure is in the seal ring region and embedded in the first insulating layer and the second insulating layer, wherein the first seal ring structure includes a stack of metal layers. The second seal ring structure is in the seal ring region and embedded in the first insulating layer, wherein the second seal ring structure includes a polysilicon ring structure. The passivation layer is on the second insulating layer and the first seal ring structure.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: June 23, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Ting-You Lin, Chi-Li Tu, Shin-Cheng Lin, Yu-Hao Ho, Cheng-Tsung Wu
  • Patent number: 10662674
    Abstract: A driving assembly of an electronic lock includes a circuit board, a motor, and an actuating cam. The abutting plate has a stopper portion and an accommodating opening. The actuating cam rotate into the accommodating opening so as to drive the abutting plate moving back and forth in a straight line. A latch assembly includes a locking column, and a buckling slot is provided at an outer periphery of the locking column. The stopper group includes a tongue pillar, a first resilience component and a tongue bolt. The tongue pillar is inserted in the buckling slot. The abutting plate moves back and forth that makes the stop portion to selectively block the tongue bolt.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: May 26, 2020
    Assignee: REAL LOCKS & SECURITY CO., LTD.
    Inventor: Hsi-Hao Ho
  • Publication number: 20200137541
    Abstract: A dual-system lock includes a lockset including a combination lock and a near field communication. The combination lock includes a contact. The near field communication includes a contacting pin. A mobile apparatus transmits a signal to the near field communication. The near field communication determines and verifies whether a verification code of the mobile apparatus is correct or not. If the near field communication determines that the verification code of the mobile apparatus is correct, the contacting pin of the near field communication is connected and contacted to the contact of the combination lock, and the near field communication transmits a message including a number to the mobile apparatus, wherein the number is a correct unlocking number. If the near field communication determines that the verification code of the mobile apparatus is incorrect, the near field communication does not transmit the message to the mobile apparatus.
    Type: Application
    Filed: October 13, 2019
    Publication date: April 30, 2020
    Inventor: Hsi-Hao HO
  • Publication number: 20200104042
    Abstract: An electronic device includes a keyboard module, a silicone film, a light-emitting module, and a touch module. The keyboard module has a plurality of buttons and a point stick. The silicone film has a virtual touch region. The light-emitting module is configured below the silicone film and corresponds to the virtual touch region. The light-emitting module includes a first light-emitting unit and a second light-emitting unit. The touch module is configured below the silicone film and corresponds to the virtual touch region. The touch module includes a control chip and a sensing layer. The point stick, the first light-emitting unit, the second light-emitting unit, and the sensing layer are electrically connected to the control chip, respectively.
    Type: Application
    Filed: February 18, 2019
    Publication date: April 2, 2020
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Meng-Huan Tsai, Yen-Hua Hsiao, Yun-Tung Pai, Chih-Yuan Lee, Chien-Hao Ho, Chia-Hua Wu, Kung-Ju Chen, Chia-Chi Lin, Chia-Chi Sun
  • Patent number: 10573738
    Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: February 25, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shang-Hui Tu, Chih-Jen Huang, Jui-Chun Chang, Shin-Cheng Lin, Yu-Hao Ho, Wen-Hsin Lin
  • Patent number: 10475784
    Abstract: A semiconductor structure is provided. A substrate has a first conductivity type. A first well and a second well are formed in the substrate. The first well has a second conductivity type. The second well has the first conductivity type. A doped region is formed in the first well and has the second conductivity type. A gate structure is disposed over the substrate and overlaps a portion of the first well and a portion of the second well. An insulating layer is disposed over the substrate and is spaced apart from the gate structure. A conducting wire is disposed on the insulating layer and includes a first input terminal and a first output terminal. The first input terminal is configured to receive an input voltage. The first output terminal is electrically connected to the doped region.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: November 12, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Yu-Hao Ho, Shin-Cheng Lin, Wen-Hsin Lin, Cheng-Tsung Wu
  • Publication number: 20190267455
    Abstract: An LDMOS includes a body region disposed in the substrate and having a first conductivity type; a drift region disposed in the substrate and having a second conductivity type; a source region disposed in the body region and having the second conductivity type; a drain region disposed in the drift region and having the second conductivity type; an isolation region disposed in the drift region between the source region and the drain region; a gate disposed on the body region and the drift region; a source field plate electrically connected to the source region; a drain field plate electrically connected to the drain region; and a first gate plate electrically connected to the gate. The first gate plate is correspondingly disposed above the gate. The shapes of the first gate plate and the gate are substantially the same when viewed from a top view.
    Type: Application
    Filed: February 23, 2018
    Publication date: August 29, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Wen-Hsin LIN, Yu-Hao HO, Shin-Cheng LIN, Cheng-Tsung WU
  • Patent number: 10388649
    Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type, wherein the semiconductor substrate includes a first region and a second region. The semiconductor device also includes a buried layer disposed in the first region of the semiconductor substrate and having the first conductivity type, wherein the buried layer has a dopant concentration that is greater than that of the semiconductor substrate. The semiconductor device further includes an epitaxial layer disposed on the semiconductor substrate, and a first element disposed on the first region of the semiconductor substrate, wherein the first element includes a bipolar-complementary metal oxide semiconductor (CMOS)-double diffused metal oxide semiconductor (DMOS) (BCD) transistor. In addition, the semiconductor device includes a second element disposed on the second region of the semiconductor substrate, wherein the second element includes an ultra-high voltage (UHV) transistor.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: August 20, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chien-Wei Chiu, Shin-Cheng Lin, Yu-Hao Ho
  • Publication number: 20190178004
    Abstract: A driving assembly of an electronic lock includes a circuit board, a motor, and an actuating cam. The abutting plate has a stopper portion and an accommodating opening. The actuating cam rotate into the accommodating opening so as to drive the abutting plate moving back and forth in a straight line. A latch assembly includes a locking column, and a buckling slot is provided at an outer periphery of the locking column. The stopper group includes a tongue pillar, a first resilience component and a tongue bolt. The tongue pillar is inserted in the buckling slot. The abutting plate moves back and forth that makes the stop portion to selectively block the tongue bolt.
    Type: Application
    Filed: December 8, 2017
    Publication date: June 13, 2019
    Inventor: Hsi-Hao HO
  • Publication number: 20190157442
    Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.
    Type: Application
    Filed: December 27, 2018
    Publication date: May 23, 2019
    Inventors: Shang-Hui TU, Chih-Jen HUANG, Jui-Chun CHANG, Shin-Cheng LIN, Yu-Hao HO, Wen-Hsin LIN
  • Patent number: 10295567
    Abstract: A probe module, which supports loopback test and is provided between a PCB and a DUT, includes an adapter, two probes, two inductive components provided at the adapter, and a capacitive component. The adapter has two connecting circuits. An end of each of the probes is connected to one of the connecting circuits, while another end thereof, which is a tip, contacts the DUT. Each of the inductive components has an end electrically connected to one of the connecting circuits, and another end electrically connected to the PCB through a conductive member, which is provided at the adapter, wherein two ends of the capacitive component are electrically connected to one of the connecting circuits, respectively. Whereby, the signal paths are changed by the differences between frequencies of signals, and the transmission path of high-frequency signals is effectively shortened.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: May 21, 2019
    Assignee: MPI CORPORATION
    Inventors: Wei-Cheng Ku, Hao Wei, Jun-Liang Lai, Chih-Hao Ho
  • Patent number: 10262938
    Abstract: A semiconductor structure including a substrate, a first well, a first doped region, a second well, a second doped region, a field oxide, a first conductive layer, a first insulating layer and a second conductive layer is provided. Each of the substrate and the second well has a first conductivity type. The first and second wells are formed in the substrate. The first well has a second conductivity type. The first doped region is formed in the first well and has the second conductivity type. The second doped region is formed in the second well and has the first conductivity type. The field oxide is disposed on the substrate and is disposed between the first and second doped regions. The first conductive layer overlaps the field oxide. The first insulating layer overlaps the first conductive layer. The second conductive layer overlaps the first insulating layer.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: April 16, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Cheng-Tsung Wu, Shin-Cheng Lin, Yu-Hao Ho, Wen-Hsin Lin