Abstract: Embodiments of systems, methods, and computer-readable media for real-time winding analysis for knot detection are disclosed. For example, one embodiment of the present invention includes a method having the steps of receiving a first wrapping signal indicating a first wrapping of the simulated thread around a second tool to create a first loop. The method further includes determining a first wrapping direction based at least in part on the first wrapping signal; receiving a first tightening signal indicating a pulling of a first end of the simulated thread through the first loop; determining a first half-hitch based at least in part on the first winding direction and the first tightening signal; and outputting the first half-hitch. In another embodiment, a computer-readable media includes code for a carrying out such a method.

Abstract: A probe card for transmitting power signals from a tester to two devices under test (DUTs) is provided, which includes two signal pins, two power conducting circuits, and at least a matching part. The signal pins are made of conductive materials, wherein one end of the signal pin contacts one of the DUTs. The two power conducting circuits are electrically connected to the two signal pins respectively to transmit the power signals to the DUTs. One of two ends of the power conducting circuits is connected to the signal pins; the other end of the power conducting circuits is electrically connected to the tester. The matching part is electrically connected to the power conducting circuit in parallel to lower a resistance of the power conducting circuit below a predetermined value, or to lower a percentage error of resistance of the power conducting circuit below a predetermined percentage error.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate of a first conductivity type and an epitaxial structure of the first conductivity type disposed on the substrate. The semiconductor device further includes a well region having a first doping concentration of a second conductivity type disposed in the epitaxial structure and the substrate. The semiconductor device further includes a drain region and a source region respectively formed in the epitaxial structure inside and outside of the well region. The semiconductor device further includes a body region of the first conductivity type disposed under the source region, and a pair of first and second doped regions disposed in the well region between the drain region and the source region. The first and second doped regions extend outside of the well region and toward the body region.

Abstract: A testing jig includes a substrate, a carrier provided on the substrate, two conductive members made of a conductive material, and a compensation member made of a conductive material. The substrate has a signal circuit and a grounding circuit thereon. The carrier has a base board made of an insulating material and a conductive circuit made of a conductive material provided thereon. The base board has a signal perforation aligning with the signal circuit, a grounding perforation aligning with the grounding circuit, and multiple compensation holes. The conductive members both have an end exposed out of the carrier, and are respectively fitted in the signal perforation and the grounding perforation to make another end thereof contact the signal circuit or the grounding circuit. The compensation member is fitted in one of the compensation holes to be electrically connected to the conductive member in the grounding perforation through the conductive circuit.

Abstract: An ultra-low power transmitter applied in multi-channel frequency shift keying (FSK) communication is provided. The transmitter includes a fixed-frequency generation device, a low-frequency frequency synthesizer, and an injection locking device. The fixed-frequency generation device provides a reference frequency to the low-frequency frequency synthesizer. The frequency synthesizer divides the reference frequency with corresponding divisors for generating a plurality of divided frequency signals. Then, the divided frequency signals are injected into the injection locking device. The injection locking device will lock at the average frequency of previously mentioned divided frequencies. Wherein, the injection locking device filters the high frequency noise, which is produced by the frequency synthesizer, at the time of the injection locking. The ultra-low power transmitter obtains a high-frequency transmitted signal by using the frequency-locked signal.

Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.

Abstract: A high-frequency cantilever type probe card includes a base board, a probe base provided on the base board, two probes, and a capacitor having opposite ends electrically connected to the probes respectively. The probe base is made of an insulating material, and the probes are made of a conductive material. Each of the probes has an arm and a tip, wherein the arm is connected to the probe base, and the tip is adapted to contact a pad of a DUT. When the DUT generates a testing signal with a high frequency, and the testing signal is transmitted to one of the probes, the capacitor, and the other one of the probes in sequence, and then transmitted back to the DUT.

Abstract: A multilayer circuit board includes a first substrate and a second substrate in stack. The first substrate first substrate a first pad, and a first circuit, wherein the first circuit is embedded in the first substrate, and the first pad is electrically connected to the first circuit. The second substrate has a first through hole, a second pad, and a second circuit, wherein the first through hole is opened at both sides of the second substrate, and the first pad of the first substrate is in the first through hole; the second circuit is embedded in the second substrate, and the second pad is electrically connected to the second circuit. The pads on each substrate are exposed by the through hole(s) of the above substrate(s) to shorten the null sections of the interconnectors and reduce the interference from the null sections.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate of a first conductivity type and an epitaxial structure of the first conductivity type disposed on the substrate. The semiconductor device further includes a well region having a first doping concentration of a second conductivity type disposed in the epitaxial structure and the substrate. The semiconductor device further includes a drain region and a source region respectively formed in the epitaxial structure inside and outside of the well region. The semiconductor device further includes a body region of the first conductivity type disposed under the source region, and a pair of first and second doped regions disposed in the well region between the drain region and the source region. The first and second doped regions extend outside of the well region and toward the body region.

Abstract: A multilayer circuit board includes a first substrate and a second substrate in stack. The first substrate is provided with a first pad, a second pad, and a first sub-circuit. The first pad and the second pad are electrically connected to the first sub-circuit. The second substrate has a top surface, a bottom surface, and an opening. The bottom surface of the second substrate is attached to the top surface of the first substrate. The opening extends from the top surface to the bottom surface of the second substrate. The first pad of the first substrate is in the opening of the second substrate; the second pad of the first substrate is not covered by the second substrate. The second substrate further provided with a pad on the top surface and a second sub-circuit electrically connected to the pad of the second substrate.

Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate of a first conductivity type and an epitaxial structure of the first conductivity type disposed on the substrate. The semiconductor device further includes a well region having a first doping concentration of a second conductivity type disposed in the epitaxial structure and the substrate. The semiconductor device further includes a drain region and a source region respectively formed in the epitaxial structure inside and outside of the well region. The semiconductor device further includes a body region of the first conductivity type disposed under the source region, and a pair of first and second doped regions disposed in the well region between the drain region and the source region. The first and second doped regions extend outside of the well region and toward the body region.

Abstract: A probe card includes a connecting circuit board, a connector, and a probe. The connecting circuit board includes a substrate having a signal via and a plurality of ground vias, a signal feeding structure disposed on the substrate, and a connecting layer having the connector disposed thereon. The signal feeding structure includes a signal feeding pad and a ground pad, which is connected to the ground via, and has a matching compensation opening having a first side and a second side wider than the first side. The signal feeding pad does not contact the ground pad, and has a first end and a second end wider than the first end. The second end is connected to the signal via. The connecting layer has a signal connecting portion connected to the signal via, and a ground connecting portion connected to the ground vias. The probe is connected to the first end.

Abstract: A probe card includes a connecting circuit board, a connector, and a probe. The connecting circuit board includes a substrate having a signal via and a plurality of ground vias, a signal feeding structure disposed on the substrate, and a connecting layer having the connector disposed thereon. The signal feeding structure includes a signal feeding pad and a ground pad, which is connected to the ground via, and has a matching compensation opening having a first side and a second side wider than the first side. The signal feeding pad does not contact the ground pad, and has a first end and a second end wider than the first end. The second end is connected to the signal via. The connecting layer has a signal connecting portion connected to the signal via, and a ground connecting portion connected to the ground vias. The probe is connected to the first end.

Abstract: The present disclosure provides a semiconductor device, including a semiconductor substrate, an epitaxial structure, a well region, a drain region and a source region respectively formed in the epitaxial structure inside and outside of the well region. At least one set of first, second and third heavily doped regions formed in the well region between source and drain regions, wherein the first, second and third heavily doped regions are adjoined sequentially from bottom to top. A gate structure disposed over the epitaxial structure. The present disclosure also provides a method for manufacturing the semiconductor device.

Abstract: A simulator trains for hemorrhage control using hemostatic agents, tourniquets, and/or other hemorrhage control techniques in a simulator that works with a wide variety of existing human surrogates. The simulator merges a live video feed of the surrogate and trainee's hands (or objects interacting with the surrogate) with a computer-generated visual representation of the wound and hemorrhaging blood to provide an immersive display experience to the trainee without requiring different surrogates for different simulated wounds. The trainee may wear pulse-generating glove(s) that simulate the patient's pulse where the trainee's finger tip contacts the surrogate. A sensorized substrate (e.g., load sensors, haptic output generators) may automatically be moved between the trainee and the surrogate to sense interaction with the surrogate and provide haptic feedback. The substrate may replace the surrogate altogether. The simulator may alternatively simulate events and objects other than wounds and humans.

Abstract: The present disclosure provides a semiconductor device, including a semiconductor substrate, an epitaxial structure, a well region, a drain region and a source region respectively formed in the epitaxial structure inside and outside of the well region. At least one set of first, second and third heavily doped regions formed in the well region between source and drain regions, wherein the first, second and third heavily doped regions are adjoined sequentially from bottom to top. A gate structure disposed over the epitaxial structure. The present disclosure also provides a method for manufacturing the semiconductor device.

Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate of a first conductivity type and an epitaxial structure of the first conductivity type disposed on the substrate. The semiconductor device further includes a well region having a first doping concentration of a second conductivity type disposed in the epitaxial structure and the substrate. The semiconductor device further includes a drain region and a source region respectively formed in the epitaxial structure inside and outside of the well region. The semiconductor device further includes a body region of the first conductivity type disposed under the source region, and a pair of first and second doped regions disposed in the well region between the drain region and the source region. The first and second doped regions extend outside of the well region and toward the body region.

Abstract: A testing jig includes a substrate, a carrier provided on the substrate, two conductive members made of a conductive material, and a compensation member made of a conductive material. The substrate has a signal circuit and a grounding circuit thereon. The carrier has a base board made of an insulating material and a conductive circuit made of a conductive material provided thereon. The base board has a signal perforation aligning with the signal circuit, a grounding perforation aligning with the grounding circuit, and multiple compensation holes. The conductive members both have an end exposed out of the carrier, and are respectively fitted in the signal perforation and the grounding perforation to make another end thereof contact the signal circuit or the grounding circuit. The compensation member is fitted in one of the compensation holes to be electrically connected to the conductive member in the grounding perforation through the conductive circuit.