Patents by Inventor Henry Descalzo Bathan

Henry Descalzo Bathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8637394
    Abstract: An integrated circuit package system includes: forming a flex bump over an integrated circuit device structure, the flex bump having both a base portion and an offset portion over the base portion; forming a first ball bond of a first internal interconnect over the offset portion; and encapsulating the integrated circuit device structure, the flex bump, and the first internal interconnect.
    Type: Grant
    Filed: July 5, 2007
    Date of Patent: January 28, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Jairus Legaspi Pisigan, Henry Descalzo Bathan, Arnel Trasporto, Jeffrey D. Punzalan
  • Patent number: 8617933
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead having a lead overhang at an obtuse angle to a lead top side and having a lead ridge protruding from a lead non-horizontal side, the lead overhang having a lead overhang-undercut side at an acute angle to a lead overhang non-horizontal side; forming a lead conductive cap completely covering the lead overhang non-horizontal side and the lead top side; forming a package paddle adjacent the lead; mounting an integrated circuit over the package paddle; and forming an encapsulation over the integrated circuit, the package paddle, and the lead.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: December 31, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Emmanuel Espiritu, Dioscoro A. Merilo
  • Patent number: 8604596
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead frame having a hole, a lead extension, and an exterior pad under the lead extension with the hole abutting the lead extension; connecting an electrical interconnect between an integrated circuit and the lead extension; forming an encapsulation over the integrated circuit and surrounding the electrical interconnect and through the hole; and removing a bottom portion of the lead frame resulting in a stand-off lead from the lead extension with the exterior pad on the stand-off lead.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: December 10, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Emmanuel Espiritu, Henry Descalzo Bathan
  • Patent number: 8592252
    Abstract: A semiconductor wafer contains a plurality of semiconductor die. The semiconductor wafer is diced to separate the semiconductor die. The semiconductor die are transferred onto a carrier. A die extension region is formed around a periphery of the semiconductor die on the carrier. The carrier is removed. A plurality of through hole vias (THV) is formed in first and second offset rows in the die extension region. A conductive material is deposited in the THVs. A first RDL is formed between contact pads on the semiconductor die and the THVs. A second RDL is formed on a backside of the semiconductor die in electrical contact with the THVs. An under bump metallization is formed in electrical contact with the second RDL. Solder bumps are formed on the under bump metallization. The die extension region is singulated to separate the semiconductor die.
    Type: Grant
    Filed: August 18, 2010
    Date of Patent: November 26, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Lionel Chien Hui Tay, Arnel Senosa Trasporto
  • Patent number: 8569872
    Abstract: An integrated circuit package system includes: providing a die-pad with a predefined slot and an integrated circuit attached to the die-pad; connecting the integrated circuit to the die-pad with a bond wire; encapsulating the integrated circuit and the bond wire with an encapsulation; and partitioning the die-pad with partial saw isolation grooves along a single axis, and into a side pad, and a die attach pad.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: October 29, 2013
    Assignee: STATS ChipPAC Ltd.
    Inventors: Henry Descalzo Bathan, Il Kwon Shim, Zigmund Ramirez Camacho, Philip Lyndon Cablao, Jose Alvin Caparas
  • Patent number: 8558369
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a post of multiple plating layers having a base end with an inward protrusion, a connect riser, and a top end opposite the base end; positioning an integrated circuit device having a perimeter end facing the connect riser and the inward protrusion; attaching a bond wire directly on the inward protrusion and the integrated circuit device; and applying an encapsulation over the integrated circuit device, the bond wire, the inward protrusion, and around the post, the encapsulation exposing a portion of the base end and the top end of the post.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: October 15, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Frederick Rodriguez Gahilig, Jairus Legaspi Pisigan
  • Patent number: 8536690
    Abstract: A method of manufacture of an integrated circuit packaging system includes: attaching a semiconductor die to a die pad of a leadframe; forming a cap layer on top of the semiconductor die for acting as a ground plane or a power plane; and connecting the semiconductor die to the cap layer through a cap bonding wire.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: September 17, 2013
    Assignee: STATS CHIPPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Lionel Chien Hui Tay, Henry Descalzo Bathan, Guruprasad Badakere Govindaiah
  • Patent number: 8508026
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a connection structure having a component pad, an outer pad, and an inner pad, the inner pad between the component pad and the outer pad; forming a support structure between the inner pad and the outer pad; mounting an integrated circuit device over the component pad; attaching an interconnect to the integrated circuit device and the outer pad, the interconnect above the inner pad and supported by the support structure; and applying an encapsulation over the connection structure, the interconnect, and the integrated circuit device.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: August 13, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Emmanuel Espiritu, Henry Descalzo Bathan
  • Patent number: 8502358
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a base structure having an intermediate lead with an intermediate concave side and an intermediate convex side, a peripheral lead with a peripheral concave side and a peripheral convex side, and a paddle with a paddle concave side and a paddle convex side; applying an inner multi-layer finish directly on the intermediate concave side, the peripheral concave side, and the paddle concave side; applying an outer multi-layer finish directly on the intermediate convex side, the peripheral convex side, and the paddle convex side; mounting an integrated circuit device over the inner multi-layer finish; attaching an interconnect directly to the inner multi-layer finish on the peripheral concave side and directly to integrated circuit device; and applying an encapsulation over the integrated circuit device, the interconnect, and the base structure, with the outer multi-layer finish exposed from the encapsulation.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: August 6, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Emmanuel Espiritu
  • Patent number: 8502371
    Abstract: An integrated circuit package system including: forming a die pad, wherein the die pad has a tiebar at a corner; forming a lead wherein the lead is connected to the tiebar; connecting an integrated circuit die to the die pad; and forming an encapsulation, having an edge, over the integrated circuit die with the lead extending from and beyond the edge.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: August 6, 2013
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Lionel Chien Hui Tay, Jairus Legaspi Pisigan, Henry Descalzo Bathan
  • Patent number: 8502357
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a package lead having a retention structure around a perimeter of the package lead with a first concave surface, a ridge, and a second concave surface; forming a die attach paddle adjacent the package lead and having an another retention structure around a perimeter of the die attach paddle with an another first concave surface, an another ridge, and an another second concave surface; attaching an integrated circuit die to the die attach paddle; connecting a conductive connector to the integrated circuit die and the package lead; and applying an encapsulation over the integrated circuit die, the encapsulation conformed to the retention structure and exposing a portion of the package lead.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: August 6, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Emmanuel Espiritu, Henry Descalzo Bathan
  • Patent number: 8493748
    Abstract: A packaging system comprising: forming terminal leads; configuring a cavity by partially encapsulating the terminal leads with a compound; attaching an integrated circuit device, a micro-electromechanical system, a micro-mechanical system, or a combination thereof in the cavity; and bonding a cover to the terminal leads for enclosing the cavity.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: July 23, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Lionel Chien Hui Tay, Jeffrey D. Punzalan
  • Patent number: 8482109
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead having a peripheral contact layer surrounding the peripheral lead with a non-horizontal side exposed from the peripheral contact layer; forming an inner lead and a paddle non-planar with the peripheral lead; mounting an integrated circuit to the paddle; and forming an encapsulation covering the integrated circuit and exposing the inner lead, the paddle, and the non-horizontal side.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: July 9, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Emmanuel Espiritu
  • Publication number: 20130154115
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead having a lead bottom body, a lead top body, and a lead top conductive layer directly on the lead top body, the lead top conductive layer having a top protrusion and a top non-vertical portion, the lead bottom body having a horizontally contiguous structure; connecting an integrated circuit to the top protrusion; and forming an encapsulation covering the integrated circuit and exposing a top non-vertical upper side of the top non-vertical portion.
    Type: Application
    Filed: December 15, 2011
    Publication date: June 20, 2013
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Emmanuel Espiritu
  • Patent number: 8455993
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a first lead adjacent and staggered to a second lead, the first lead having a first external connection portion with a first external conductive layer and a first internal connection portion, the first external connection portion oriented laterally outwards from the first internal connection portion, and the second lead having a second external connection portion with a second external conductive layer and a second internal connection portion; connecting an integrated circuit device with the first internal connection portion and with the second internal connection portion; forming an encapsulation over the integrated circuit device with the first lead and the second lead exposed; and forming a solder mask on the encapsulation, on the first lead, and on the second lead with the first external conductive layer and the second external conductive layer exposed from the solder mask.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: June 4, 2013
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Emmanuel Espiritu
  • Patent number: 8420508
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base panel having a first side with a cavity and a second side opposite the first side; connecting an integrated circuit device and the first side; applying a resist mask having an opening on the second side, the opening offset from the cavity; forming a bump contact in the opening; applying an encapsulation in the cavity over the integrated circuit device and the first side; and forming a package lead by removing a portion of the base panel under the cavity, a flared tip of the package lead intersecting a base side of the encapsulation.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: April 16, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Emmanuel Espiritu
  • Patent number: 8420447
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: leads and a paddle; a first encapsulant molded between the leads and the paddle, the first encapsulant thinner than the leads; a non-conductive layer over the paddle; and conductive traces directly on the leads, the first encapsulant, and the non-conductive layer.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: April 16, 2013
    Assignee: STATS ChipPAC Ltd.
    Inventors: Lionel Chien Hui Tay, Henry Descalzo Bathan, Zigmund Ramirez Camacho
  • Patent number: 8415205
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead having an upper portion and a bottom portion with a first overhang portion from a top surface of the upper portion and the lead also having serrations along upper vertical sides intersecting the top surface; forming an upper contact plate on the top surface; forming a bottom contact plate on a bottom surface of the bottom portion; attaching an integrated circuit die over the upper portion; and encapsulating the upper portion and the integrated circuit die with an encapsulation leaving the bottom portion exposed.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: April 9, 2013
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Emmanuel Espiritu
  • Publication number: 20130075883
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead having a peripheral contact layer surrounding the peripheral lead with a non-horizontal side exposed from the peripheral contact layer; forming an inner lead and a paddle non-planar with the peripheral lead; mounting an integrated circuit to the paddle; and forming an encapsulation covering the integrated circuit and exposing the inner lead, the paddle, and the non-horizontal side.
    Type: Application
    Filed: September 22, 2011
    Publication date: March 28, 2013
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Emmanuel Espiritu
  • Patent number: 8404524
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package paddle having a hole, a recess, and a pad, the hole over the recess; mounting an integrated circuit to the package paddle; forming a lead having a bottom surface coplanar with a bottom surface of the pad, the lead isolated from the package paddle; attaching connectors directly on the integrated circuit, the lead, and the package paddle; and forming an encapsulation covering the integrated circuit and within the hole and the recess.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: March 26, 2013
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Emmanuel Espiritu