Patents by Inventor Henry Descalzo Bathan

Henry Descalzo Bathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8399991
    Abstract: A semiconductor wafer contains a plurality of semiconductor die. The semiconductor wafer is diced to separate the semiconductor die. The semiconductor die are transferred onto a carrier. A die extension region is formed around a periphery of the semiconductor die on the carrier. The carrier is removed. A plurality of through hole vias (THV) is formed in first and second offset rows in the die extension region. A conductive material is deposited in the THVs. A first RDL is formed between contact pads on the semiconductor die and the THVs. A second RDL is formed on a backside of the semiconductor die in electrical contact with the THVs. An under bump metallization is formed in electrical contact with the second RDL. Solder bumps are formed on the under bump metallization. The die extension region is singulated to separate the semiconductor die.
    Type: Grant
    Filed: August 18, 2010
    Date of Patent: March 19, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Lionel Chien Hui Tay, Arnel Senosa Trasporto
  • Patent number: 8389332
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead frame having a die attach paddle, an isolated pad, and a connector; attaching an integrated circuit die to the die attach paddle and the connector; forming an encapsulation over the integrated circuit die, the connector, the die attach paddle, and the isolated pad; and singulating the connector and the die attach paddle whereby the isolated pads are electrically isolated.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: March 5, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Lionel Chien Hui Tay, Jose Alvin Caparas
  • Patent number: 8377750
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a base structure having a die paddle, an outer lead, and an inner lead between the die paddle and the outer lead, with a pre-plated finish on a base structure system side of the base structure; mounting an integrated circuit device to a side of the die paddle opposite the paddle system side; attaching an interconnect to the integrated circuit device and a side of the inner lead opposite the inner lead system side; applying an encapsulation around the integrated circuit device, the interconnect, and the base structure with the pre-plated finish exposed from the encapsulation; and forming an inward channel in the encapsulation to electrically isolate the inner lead.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: February 19, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Dioscoro A. Merilo, Henry Descalzo Bathan
  • Patent number: 8362601
    Abstract: A method of manufacture of a wire-on-lead package system includes: providing a die attach paddle with paddle extensions distributed along the periphery of the die attach paddle, providing leadfingers surrounding the die attach paddle, attaching a semiconductor die to the die attach paddle wherein the semiconductor die is larger than the die attach paddle, and connecting bond wires between the semiconductor die and the leadfingers and between the semiconductor die and the paddle extensions.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: January 29, 2013
    Assignee: Stats Chippac Ltd
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Jeffrey D. Punzalan, Lionel Chien Hui Tay
  • Publication number: 20120326285
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a package paddle; forming a lead adjacent to the package paddle; depositing a lead conductive cap on the lead, the lead conductive cap includes a nickel layer having a thickness between 2.55 ?m to 8.00 ?m deposited on the lead, a palladium layer deposited on the nickel layer, and a gold layer deposited on the palladium layer; mounting an integrated circuit over the package paddle; attaching an electrical connector between the lead conductive cap and the integrated circuit; and forming an encapsulation over the integrated circuit, a portion of the lead, and a portion of the package paddle.
    Type: Application
    Filed: June 23, 2011
    Publication date: December 27, 2012
    Inventors: Emmanuel Espiritu, Elizar Andres, Henry Descalzo Bathan, Zigmund Ramirez Camacho
  • Patent number: 8338233
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a base lead having an outer protrusion and an inner protrusion with a recess in between; forming a stack lead having an elongated portion; mounting a base integrated circuit over the inner protrusion or under the elongated portion; mounting the stack lead over the base lead and the base integrated circuit; connecting a stack integrated circuit and the stack lead with the stack integrated circuit over the base integrated circuit; and encapsulating at least a portion of both the base integrated circuit and the stack integrated circuit with the base lead and the stack lead exposed.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: December 25, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Jairus Legaspi Pisigan, Henry Descalzo Bathan
  • Patent number: 8334584
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base array having terminals and an open region; attaching a coverlay layer directly on the base array; placing a component in the open region and directly on the coverlay layer; forming an encapsulation over the base array and the component; removing the coverlay layer to leave a plane of the terminals and a plane of the component partially exposed and substantially coplanar; and removing a portion of the base array between the terminals, the terminals electrically isolated.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: December 18, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Emmanuel Espiritu
  • Patent number: 8334171
    Abstract: A method of manufacture of a package system includes: providing a base package substrate having conductive elements; providing an internal stacking module having a semiconductor die mounted on a package substrate and a first encapsulant surrounding at least portions of the semiconductor die and the package substrate; covering at least portions of the first encapsulant in the internal stacking module with an electromagnetic interference shield, the electromagnetic interference shield shaped to have an outside face; mounting the internal stacking module over the base package substrate with the outside face of the electromagnetic interference shield facing the base package substrate; and encapsulating at least portions of the internal stacking module, the electromagnetic interference shield, and the base package substrate using a second encapsulant.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: December 18, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Reza Argenty Pagaila, Zigmund Ramirez Camacho, Henry Descalzo Bathan
  • Publication number: 20120299196
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead having a lead overhang at an obtuse angle to a lead top side and having a lead ridge protruding from a lead non-horizontal side, the lead overhang having a lead overhang-undercut side at an acute angle to a lead overhang non-horizontal side; forming a lead conductive cap completely covering the lead overhang non-horizontal side and the lead top side; forming a package paddle adjacent the lead; mounting an integrated circuit over the package paddle; and forming an encapsulation over the integrated circuit, the package paddle, and the lead.
    Type: Application
    Filed: May 27, 2011
    Publication date: November 29, 2012
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Emmanuel Espiritu, Dioscoro A. Merilo
  • Patent number: 8304921
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a planar support structure having a cavity; forming a terminal within the cavity with the terminal coplanar with the planar support structure; forming a conductive pathway on the terminal and the planar support structure with the conductive pathway having a route portion and an interconnect attach portion at the end of the route portion; connecting a device and the interconnect attach portion with the interconnect attach portion towards the device; and forming an encapsulation over the planar support structure covering the conductive pathway and the device.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: November 6, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Allan P. Ilagan, Philip Lyndon Cablao
  • Patent number: 8304337
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a device over a substrate including a bond wire pad row located between a perimeter of the substrate and the device; configuring the bond wire pad row to include three sided bond wire pads that horizontally overlap; and forming an interconnection between the device and the bond wire pad row.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: November 6, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Henry Descalzo Bathan, Jairus Legaspi Pisigan, Zigmund Ramirez Camacho
  • Patent number: 8304869
    Abstract: An integrated circuit package on package system includes: providing a lead having a wire-bonded die with a bond wire connected thereto; mounting a fan-in interposer over the wire-bonded die and the bond wire; connecting the fan-in interposer to the lead with the bond wires; and encapsulating the wire-bonded die, bond wires, and the fan-in interposer with an encapsulation leaving a portion of the fan-in interposer exposed.
    Type: Grant
    Filed: August 1, 2008
    Date of Patent: November 6, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Jairus Legaspi Pisigan, Lionel Chien Hui Tay, Henry Descalzo Bathan
  • Publication number: 20120261808
    Abstract: A method of manufacture of an integrated circuit package system includes: attaching a first die to a first die pad; connecting electrically a second die to the first die through a die interconnect positioned between the first die and the second die; connecting a first lead adjacent the first die pad to the first die; connecting a second lead to the second die, the second lead opposing the first lead and adjacent the second die; and providing a molding material around the first die, the second die, the die interconnect, the first lead and the second lead, with a portion of the first lead exposed.
    Type: Application
    Filed: June 28, 2012
    Publication date: October 18, 2012
    Inventors: Zigmund Ramirez Camacho, Dioscoro A. Merilo, Henry Descalzo Bathan, Lionel Chien Hui Tay
  • Publication number: 20120241947
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead frame having a hole, a lead extension, and an exterior pad under the lead extension with the hole abutting the lead extension; connecting an electrical interconnect between an integrated circuit and the lead extension; forming an encapsulation over the integrated circuit and surrounding the electrical interconnect and through the hole; and removing a bottom portion of the lead frame resulting in a stand-off lead from the lead extension with the exterior pad on the stand-off lead.
    Type: Application
    Filed: March 24, 2011
    Publication date: September 27, 2012
    Inventors: Zigmund Ramirez Camacho, Emmanuel Espiritu, Henry Descalzo Bathan
  • Publication number: 20120241968
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a post of multiple plating layers having a base end with an inward protrusion, a connect riser, and a top end opposite the base end; positioning an integrated circuit device having a perimeter end facing the connect riser and the inward protrusion; attaching a bond wire directly on the inward protrusion and the integrated circuit device; and applying an encapsulation over the integrated circuit device, the bond wire, the inward protrusion, and around the post, the encapsulation exposing a portion of the base end and the top end of the post.
    Type: Application
    Filed: March 25, 2011
    Publication date: September 27, 2012
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Frederick Rodriguez Dahilig, Jairus Legaspi Pisigan
  • Publication number: 20120241928
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: leads and a paddle; a first encapsulant molded between the leads and the paddle, the first encapsulant thinner than the leads; a non-conductive layer over the paddle; and conductive traces directly on the leads, the first encapsulant, and the non-conductive layer.
    Type: Application
    Filed: March 23, 2011
    Publication date: September 27, 2012
    Inventors: Lionel Chien Hui Tay, Henry Descalzo Bathan, Zigmund Ramirez Camacho
  • Publication number: 20120241983
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead; placing an integrated circuit device, having an external connector, adjacent to and electrically isolated from the lead; mounting an integrated circuit over the lead and the integrated circuit device with the integrated circuit electrically isolated from the integrated circuit device; and forming a package encapsulation, having an encapsulation base, over the lead, the integrated circuit, and the integrated circuit device with the lead and the external connector exposed from the encapsulation base.
    Type: Application
    Filed: March 21, 2011
    Publication date: September 27, 2012
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Jairus Legaspi Pisigan
  • Publication number: 20120241926
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead; mounting an integrated circuit adjacent the lead; molding an encapsulation encapsulating the lead and the integrated circuit; and forming a leveling standoff protruded from the same surface of the encapsulation as the lead with the integrated circuit between the lead and the leveling standoff electrically isolated from the lead and the integrated circuit.
    Type: Application
    Filed: March 23, 2011
    Publication date: September 27, 2012
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Emmanuel Espiritu
  • Publication number: 20120241931
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a die paddle and a lead adjacent to the die paddle; mounting an integrated circuit, having a bond pad, over the die paddle; forming a bonding interconnect on the bond pad; embedding a circuit end of an internal interconnect in the bonding interconnect; and connecting a lead end of the internal interconnect to the lead.
    Type: Application
    Filed: March 23, 2011
    Publication date: September 27, 2012
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Jairus Legaspi Pisigan, Rachel Layda Abinan
  • Publication number: 20120241966
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: an L-plated lead; a die conductively connected to the L-plated lead; and an encapsulant encapsulating the L-plated lead and the die.
    Type: Application
    Filed: March 23, 2011
    Publication date: September 27, 2012
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Lionel Chien Hui Tay