Patents by Inventor Henry Descalzo Bathan

Henry Descalzo Bathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8273602
    Abstract: An integrated circuit package system comprising: fabricating a package base including: forming a lead frame, coupling a first integrated circuit device under the lead frame, coupling a second integrated circuit device over the first integrated circuit device, and molding an enclosure on the lead frame, the first integrated circuit device, and the second integrated circuit device for forming an integration port; and coupling a third integrated circuit device on the integration port.
    Type: Grant
    Filed: March 11, 2008
    Date of Patent: September 25, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Henry Descalzo Bathan, Lionel Chien Hui Tay, Zigmund Ramirez Camacho, Jose Alvin Caparas
  • Patent number: 8258609
    Abstract: An integrated circuit package system is provided including forming a paddle having an integrated circuit die thereover, an outer lead, and an inner lead between the paddle and the outer lead. The integrated circuit package system is also provided including placing a lead support over the inner lead without traversing to an inner body bottom side of the inner lead, connecting the integrated circuit die and the inner lead, and encapsulating the inner lead having the lead support thereover and the inner lead exposed.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: September 4, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Jose Alvin Caparas, Arnel Trasporto
  • Patent number: 8252666
    Abstract: A semiconductor wafer contains a plurality of semiconductor die. The semiconductor wafer is diced to separate the semiconductor die. The semiconductor die are transferred onto a carrier. A die extension region is formed around a periphery of the semiconductor die on the carrier. The carrier is removed. A plurality of through hole vias (THV) is formed in first and second offset rows in the die extension region. A conductive material is deposited in the THVs. A first RDL is formed between contact pads on the semiconductor die and the THVs. A second RDL is formed on a backside of the semiconductor die in electrical contact with the THVs. An under bump metallization is formed in electrical contact with the second RDL. Solder bumps are formed on the under bump metallization. The die extension region is singulated to separate the semiconductor die.
    Type: Grant
    Filed: August 18, 2010
    Date of Patent: August 28, 2012
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Lionel Chien Hui Tay, Arnel Senosa Trasporto
  • Patent number: 8241965
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package paddle; forming a pad extension having a spacing to the package paddle; forming a lead adjacent the pad extension, the pad extension between the package paddle and the lead; forming a conductive layer directly on and between the package paddle and the pad extension; and connecting an integrated circuit to the pad extension and the lead, the integrated circuit over the package paddle.
    Type: Grant
    Filed: August 18, 2010
    Date of Patent: August 14, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Henry Descalzo Bathan, Flynn Carson, Zigmund Ramirez Camacho, Emmanuel Espiritu
  • Patent number: 8236607
    Abstract: A method of manufacture an integrated circuit packaging system includes: providing a substrate; attaching a base component to the substrate by a first interconnect; attaching a stack component connected by a second interconnect to the substrate and partially over the base component, the second interconnect different from the first interconnect; molding an encapsulation over the base component, the first interconnect, the stack component, and the second interconnect; and removing the substrate to partially expose the first interconnect and the second interconnect from the encapsulation.
    Type: Grant
    Filed: June 19, 2009
    Date of Patent: August 7, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Jairus Legaspi Pisigan
  • Patent number: 8212342
    Abstract: A method of manufacture of an integrated circuit package system includes providing a first frame having a first removable backing element connecting a first die attach pad and a first plurality of terminal leads. A first die is attached to the first die attach pad. A substrate is provided. A second die is attached to the substrate. The first die is attached to the second die with a plurality of die interconnects. The first removable backing element is removed after connecting the first die to the second die.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: July 3, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Dioscoro A. Merilo, Henry Descalzo Bathan, Lionel Chien Hui Tay
  • Patent number: 8207600
    Abstract: An integrated circuit package system is provided including forming a lead frame includes forming a mold gate, providing a first surface, and providing a second surface opposite the first surface; and forming angled gate sides facing each other in the mold gate between the first surface and the second surface.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: June 26, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Henry Descalzo Bathan, Jeffrey D. Punzalan, Abelardo Hadap Advincula, Jose Alvin Caparas
  • Patent number: 8203214
    Abstract: An integrated circuit package in package system includes a package in package lead with a package in package lead surface substantially planar, attaching a first integrated circuit package having a first encapsulant surface substantially coplanar with the package in package lead surface, attaching a second integrated circuit near the first integrated circuit package, and forming a package in package encapsulant over the first integrated circuit package and the second integrated circuit.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: June 19, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Lionel Chien Hui Tay, Jeffrey D. Punzalan
  • Patent number: 8203201
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a paddle, an inner post adjacent to the paddle, a jumper pad, and an outer post, with the jumper pad between the inner post and the outer post; mounting an integrated circuit over a paddle first side, the paddle first side co-planar with the outer post; connecting a first jumper interconnect between the integrated circuit and the jumper pad; connecting a second jumper interconnect between the jumper pad and the outer post; and forming an encapsulation over paddle, the integrated circuit, the first jumper interconnect, the jumper pad, and the second jumper interconnect.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: June 19, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Emmanuel Espiritu, Henry Descalzo Bathan
  • Publication number: 20120146203
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a base structure having a die paddle, an outer lead, and an inner lead between the die paddle and the outer lead, with a pre-plated finish on a base structure system side of the base structure; mounting an integrated circuit device to a side of the die paddle opposite the paddle system side; attaching an interconnect to the integrated circuit device and a side of the inner lead opposite the inner lead system side; applying an encapsulation around the integrated circuit device, the interconnect, and the base structure with the pre-plated finish exposed from the encapsulation; and forming an inward channel in the encapsulation to electrically isolate the inner lead.
    Type: Application
    Filed: December 14, 2010
    Publication date: June 14, 2012
    Inventors: Zigmund Ramirez Camacho, Dioscoro A. Merilo, Henry Descalzo Bathan
  • Publication number: 20120146192
    Abstract: A method of manufacture of an integrated circuit mounting system includes: providing a die paddle with a component side having a die mount area and a recess with more than one geometric shape; applying an adhesive on the die mount area and in a portion of the recess; and mounting an integrated circuit device with an inactive side directly on the adhesive.
    Type: Application
    Filed: December 14, 2010
    Publication date: June 14, 2012
    Inventors: Byung Joon Han, Byung Tai Do, Arnel Senosa Trasporto, Henry Descalzo Bathan
  • Publication number: 20120139121
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead having a horizontal ridge at a lead top side; forming a connection layer having an inner pad and an outer pad directly on the lead top side, the inner pad having an inner pad bottom surface; mounting an integrated circuit over the inner pad; applying a molding compound, having a molding bottom surface, over the integrated circuit, the inner pad, and the outer pad; and applying a dielectric directly on the molding bottom surface and the inner pad bottom surface.
    Type: Application
    Filed: December 6, 2010
    Publication date: June 7, 2012
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Dioscoro A. Merilo, Emmanuel Espiritu
  • Publication number: 20120139104
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead having a lead bottom side and a lead top side; applying a passivation over the lead with the lead top side exposed from the passivation; forming an interconnect structure directly on the passivation and the lead top side, the interconnect structure having an inner pad and an outer pad with a recess above the lead top side; mounting an integrated circuit over the inner pad and the passivation; and molding an encapsulation over the integrated circuit.
    Type: Application
    Filed: December 6, 2010
    Publication date: June 7, 2012
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Emmanuel Espiritu, Dioscoro A. Merilo
  • Patent number: 8193037
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead having a horizontal ridge at a lead top side; forming a connection layer having an inner pad and an outer pad directly on the lead top side, the inner pad having an inner pad bottom surface; mounting an integrated circuit over the inner pad; applying a molding compound, having a molding bottom surface, over the integrated circuit, the inner pad, and the outer pad; and applying a dielectric directly on the molding bottom surface and the inner pad bottom surface.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: June 5, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Dioscoro A. Merilo, Emmanuel Espiritu
  • Publication number: 20120133033
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a base structure having an intermediate lead with an intermediate concave side and an intermediate convex side, a peripheral lead with a peripheral concave side and a peripheral convex side, and a paddle with a paddle concave side and a paddle convex side; applying an inner multi-layer finish directly on the intermediate concave side, the peripheral concave side, and the paddle concave side; applying an outer multi-layer finish directly on the intermediate convex side, the peripheral convex side, and the paddle convex side; mounting an integrated circuit device over the inner multi-layer finish; attaching an interconnect directly to the inner multi-layer finish on the peripheral concave side and directly to integrated circuit device; and applying an encapsulation over the integrated circuit device, the interconnect, and the base structure, with the outer multi-layer finish exposed from the encapsulation.
    Type: Application
    Filed: November 30, 2010
    Publication date: May 31, 2012
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Emmanuel Espiritu
  • Publication number: 20120133036
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a connection structure having a component pad, an outer pad, and an inner pad, the inner pad between the component pad and the outer pad; forming a support structure between the inner pad and the outer pad; mounting an integrated circuit device over the component pad; attaching an interconnect to the integrated circuit device and the outer pad, the interconnect above the inner pad and supported by the support structure; and applying an encapsulation over the connection structure, the interconnect, and the integrated circuit device.
    Type: Application
    Filed: November 30, 2010
    Publication date: May 31, 2012
    Inventors: Zigmund Ramirez Camacho, Emmanuel Espiritu, Henry Descalzo Bathan
  • Publication number: 20120104585
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming signal contacts; forming a power bar having a power bar terminal, the power bar terminal formed in a staggered position relative to the signal contacts; depositing a terminal pad on the power bar terminal; depositing a contact pad on one of the signal contacts; coupling an integrated circuit die to the power bar terminal and the signal contacts; and forming a package body on the integrated circuit die.
    Type: Application
    Filed: October 28, 2011
    Publication date: May 3, 2012
    Inventors: Emmanuel Espiritu, Henry Descalzo Bathan, Zigmund Ramirez Camacho
  • Patent number: 8148208
    Abstract: A method for manufacturing an integrated circuit package system includes: providing a frame; attaching a leaded package having leads adjacent the frame wherein the leads extend towards a side opposite the frame; and applying a package encapsulant over the leaded package having the leads partially exposed opposite the frame.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: April 3, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Jairus Legaspi Pisigan, Henry Descalzo Bathan, Lionel Chien Hui Tay
  • Publication number: 20120074548
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a package paddle; forming a lead adjacent the package paddle, the lead having a lead overhang protruding from a lead non-horizontal side and a lead ridge protruding from the lead non-horizontal side; mounting an integrated circuit over the package paddle; connecting an electrical connector to the lead and the integrated circuit; and forming an encapsulation over the integrated circuit, the lead, and the package paddle, the encapsulation under the lead overhang.
    Type: Application
    Filed: September 24, 2010
    Publication date: March 29, 2012
    Inventors: Zigmund Ramirez Camacho, Emmanuel Espiritu, Henry Descalzo Bathan
  • Publication number: 20120068363
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a package paddle group having a first package paddle electrically isolated from a second package paddle; attaching an integrated circuit device on the first package paddle and the second package paddle; forming a standoff terminal adjacent the package paddle group and electrically connected to the integrated circuit device; connecting a paddle connector to the integrated circuit device and the first package paddle and another paddle connector to the integrated circuit device and the second package paddle; and forming an encapsulation over the integrated circuit device, the first package paddle, the second package paddle, and the standoff terminal, the encapsulation exposing a portion of the first package paddle, the second package paddle, and the standoff terminal.
    Type: Application
    Filed: September 16, 2010
    Publication date: March 22, 2012
    Inventors: Zigmund Ramirez Camacho, Emmanuel Espiritu, Henry Descalzo Bathan