Patents by Inventor Hiroyuki Mori

Hiroyuki Mori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11791270
    Abstract: A direct bonded heterogeneous integration (DBHi) device includes a substrate including a trench formed in a top surface of the substrate. The DBHi device further includes a first chip coupled to the substrate on a first side of the trench by a plurality of first interconnects. The DBHi device further includes a second chip coupled to the substrate on a second side of the trench by a plurality of second interconnects. The second side of the trench is arranged opposite the first side of the trench. The DBHi device further includes a bridge coupled to the first chip and to the second chip by a plurality of third interconnects such that the bridge is suspended in the trench. The DBHi device further includes a non-conductive paste material surrounding the plurality of third interconnects to further couple the bridge to the first chip and to the second chip.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: October 17, 2023
    Assignee: International Business Machines Corporation
    Inventors: Kamal K Sikka, Maryse Cournoyer, Pascale Gagnon, Charles C. Bureau, Catherine Dufort, Dale Curtis McHerron, Vijayeshwar Das Khanna, Marc A. Bergendahl, Dishit Paresh Parekh, Ravi K. Bonam, Hiroyuki Mori, Yang Liu, Paul S. Andry, Isabel De Sousa
  • Publication number: 20230311233
    Abstract: A spot welding method including: a main energization step of energizing a pair of opposing electrodes in pressure contact with both outer surfaces of a set of sheets where multiple sheet materials are stacked, thereby to cause melting between facing surfaces of the sheet materials; and a pressing variation step of, prior to the main energization step, causing a pulsation of pressing force applied to the set of sheets from the electrodes. A resin material such as an adhesive or a sealant may be interposed between the facing surfaces of at least a pair of the sheet materials. The period of the pulsation is 0.01 to 0.7 seconds. The amplitude of the pulsation is 10% to 90% with respect to a reference value of the pressing force. The set of sheets may include a first and a second steel sheet, and an aluminum alloy sheet that are stacked in order.
    Type: Application
    Filed: February 8, 2023
    Publication date: October 5, 2023
    Applicants: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hideaki MATSUOKA, Gaku Kitahara, Tatsuyuki Amago, Hiroyuki Mori, Jun Yaokawa, Kyosuke Izuno, Shuhei Ogura, Tomohiko Sekiguchi, Ayaka Kagami
  • Publication number: 20230313341
    Abstract: A copper alloy plastically-worked material comprises Mg in the amount of 10-100 mass ppm and a balance of Cu and inevitable impurities, which comprise 10 mass ppm or less of S, 10 mass ppm or less of P, 5 mass ppm or less of Se, 5 mass ppm or less of Te, 5 mass ppm or less of Sb, 5 mass ppm or less of Bi and 5 mass ppm or less of As. The total amount of S, P, Se, Te, Sb, Bi, and As is 30 mass ppm or less. The mass ratio of [Mg]/[S+P+Se+Te+Sb+Bi+As] is 0.6 or greater and 50 or less. The electrical conductivity is 97% IACS or greater. The tensile strength is 275 MPa or less. The heat-resistant temperature after draw working is 150° C. or higher.
    Type: Application
    Filed: June 30, 2021
    Publication date: October 5, 2023
    Applicant: MITSUBISHI MATERIALS CORPORATION
    Inventors: Hirotaka MATSUNAGA, Yuki ITO, Kosei FUKUOKA, Kazunari MAKI, Kenji MORIKAWA, Shinichi FUNAKI, Hiroyuki MORI
  • Publication number: 20230299067
    Abstract: Interconnecting a first chip and a second chip includes mounting the first and second chips to a chip handler having an opening and at least one support surface. Each of the first chip and the second chip has a first surface including a first set of terminals and a second surface opposite to the first surface. The first surface of the first chip and the first surface of the second chip mounted to the chip handler are supported by the at least one support surface of the chip handler. The first and second chips are placed on a chip support member with the chip handler from the second surfaces. A bridge member is inserted by a bridge handler through the opening of the chip handler to place the bridge member onto the first sets of terminals of the first and second chips that are exposed from the opening.
    Type: Application
    Filed: May 26, 2023
    Publication date: September 21, 2023
    Inventors: Akihiro Horibe, Takahito Watanabe, Toyohiro Aoki, Takashi Hisada, Hiroyuki Mori
  • Publication number: 20230296125
    Abstract: A method of manufacturing a member for fastening by joining a nut with a tubular joint portion extending from a main body formed with an internal thread to a panel with a mounting hole for the nut on an aluminum base material. The joint portion has a rotation-preventing portion with a concave and convex shaped outer peripheral surface and a guide portion extending from the rotation-preventing portion to one side. After the guide portion is inserted into the mounting hole, the nut is energized by electrodes in contact with both nut end surface sides. The nut then generates heat, and the periphery of the mounting hole is heated and softened. When the nut is pressurized with the electrodes, the rotation-preventing portion bites into the mounting hole, and the one end portion of the guide portion is swaged to become a retaining portion on one surface side of the panel.
    Type: Application
    Filed: February 3, 2023
    Publication date: September 21, 2023
    Applicants: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hideaki MATSUOKA, Gaku KITAHARA, Tatsuyuki AMAGO, Hiroyuki MORI, Jun YAOKAWA, Kyosuke IZUNO, Kohei TAKAHASHI, Tomohiko SEKIGUCHI, Ayaka KAGAMI
  • Patent number: 11735529
    Abstract: An integrated circuit package includes a substrate including at least one electrical connection to at least one of power or ground. The package further includes a bridge structure including at least one layer of conductive material and at least one layer of insulative material. The bridge structure is configured to be coupled to the substrate such that the conductive material is electrically connected to the at least one electrical connection. The bridge structure includes a side pad made of conductive material that is electrically connected to the at least one electrical connection. The side pad is in direct contact with the conductive material and with the insulative material of the bridge structure. The side pad forms an end face of the bridge structure such that the conductive material of the side pad is exposed.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: August 22, 2023
    Assignee: International Business Machines Corporation
    Inventors: Takahito Watanabe, Risa Miyazawa, Hiroyuki Mori
  • Patent number: 11735575
    Abstract: Interconnecting a first chip and a second chip by a bridge member includes a chip handler for handling the first chip and the second chip. Each of the first chip and the second chip has a first surface including a first set of terminals and a second surface opposite to the first surface. The chip handler has an opening and at least one support surface for supporting the first surfaces of the first chip and the second chip when the first chip and the second chip are mounted to the chip handler. A chip support member supports the first chip and the second chip from the second surfaces, and a bridge handler is provided for inserting the bridge member through the opening of the chip handler and for placing the bridge member onto the first sets of terminals of the first chip and the second chip.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: August 22, 2023
    Assignee: International Business Machines Corporation
    Inventors: Akihiro Horibe, Takahito Watanabe, Toyohiro Aoki, Takashi Hisada, Hiroyuki Mori
  • Patent number: 11732329
    Abstract: A copper alloy has a composition including: 70 mass ppm or more and 400 mass ppm or less of Mg; 5 mass ppm or more and 20 mass ppm or less of Ag; less than 3.0 mass ppm of P; and a Cu balance containing inevitable impurities. In the copper alloy, the electrical conductivity is 90% IACS or more, and the average value of KAM values is 3.0 or less.
    Type: Grant
    Filed: November 27, 2020
    Date of Patent: August 22, 2023
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Hirotaka Matsunaga, Yuki Ito, Hiroyuki Mori, Hiroyuki Matsukawa
  • Publication number: 20230261014
    Abstract: The present technology relates to a solid-state imaging device capable of suppressing deterioration in dark characteristics, and an electronic apparatus. The present invention is provided with: a photoelectric conversion section that performs photoelectric conversion; a charge retaining section that temporarily retains electric charge converted by the photoelectric conversion section; and a first trench formed in a semiconductor substrate between the photoelectric conversion section and the charge retaining section, the first trench being higher than the photoelectric conversion section in a depth direction of the semiconductor substrate. Alternatively, the first trench is lower than the photoelectric conversion section and higher than the charge retaining section in the depth direction of the semiconductor substrate. The present technology can be applied to, for example, a back-illuminated CMOS image sensor.
    Type: Application
    Filed: April 28, 2023
    Publication date: August 17, 2023
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Tetsuya UCHIDA, Ryoji SUZUKI, Yoshiharu KUDOH, Hiroyuki MORI, Harumi TANAKA
  • Publication number: 20230262882
    Abstract: Embodiments of present invention provide a multilayer printed circuit board. The printed circuit board includes a first conducting layer (CL) having a first measurement mark area (MMA) and a second CL having a second MMA. A first polygonal measurement mark (MM) in the first MMA and a second and a third polygonal MM in the second MMA, wherein the second polygonal MM is positioned along an extended first angle bisector bisecting a first vertex of the first polygonal MM and a first vertex of the second polygonal MM is substantially aligned with the first vertex of the first polygonal MM, and wherein the third polygonal MM is positioned along an extended second angle bisector bisecting a second vertex of the first polygonal MM and a first vertex of the third polygonal MM is substantially aligned with the second vertex of the first polygonal MM.
    Type: Application
    Filed: February 17, 2022
    Publication date: August 17, 2023
    Inventor: Hiroyuki Mori
  • Patent number: 11725258
    Abstract: This copper alloy for electronic or electric devices contains 100 mass ppm or greater and 400 mass ppm or less of Mg, 5 mass ppm or greater and 20 mass ppm or less of Ag, and less than 5 mass ppm of P with a balance being Cu and inevitable impurities, in which when a ratio of J3, in which all three grain boundaries constituting a grain boundary triple junction are special grain boundaries, to all grain boundary triple junctions is defined as NFJ3 and a ratio of J2, in which two grain boundaries constituting a grain boundary triple junction are special grain boundaries and one grain boundary constituting the grain boundary triple junction is a random grain boundary, to all grain boundary triple junctions is defined as NFJ2, an expression of 0.22<(NFJ2/(1?NFJ3))0.5?0.45 is satisfied.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: August 15, 2023
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Hirotaka Matsunaga, Yuki Ito, Hiroyuki Mori, Hiroyuki Matsukawa
  • Publication number: 20230250514
    Abstract: This copper alloy contains greater than 10 mass ppm and less than 100 mass ppm of Mg, with a balance being Cu and inevitable impurities, which comprise: 10 mass ppm or less of S, 10 mass ppm or less of P, 5 mass ppm or less of Se, 5 mass ppm or less of Te, 5 mass ppm or less of Sb, 5 mass ppm or less of Bi, and 5 mass ppm or less of As. The total amount of S, P, Se, Te, Sb, Bi, and As is 30 mass ppm or less. The mass ratio [Mg]/[S+P+Se+Te+Sb+Bi+As] is 0.6 to 50, an electrical conductivity is 97% IACS or greater. The half-softening temperature ratio TLD/TTD is greater than 0.95 and less than 1.08. The half-softening temperature TLD is 210° C. or higher.
    Type: Application
    Filed: June 30, 2021
    Publication date: August 10, 2023
    Applicant: MITSUBISHI MATERIALS CORPORATION
    Inventors: Hirotaka MATSUNAGA, Kosei FUKUOKA, Kazunari MAKI, Kenji MORIKAWA, Shinichi FUNAKI, Hiroyuki MORI
  • Publication number: 20230246444
    Abstract: It is intended to reduce errors related to an energy supply plan to be formulated. An energy supply plan formulation device includes an acquisition unit for acquiring a change of a base load of energy equipment, a determination unit for determining whether to need correction of at least one of an equipment model and a load model on the basis of the change of the base load, a correction unit for correcting at least one of the equipment model and the load model on the basis of a determination result, a demand forecasting unit for forecasting the amount of energy demand, and a supply plan formulation unit for formulating an energy supply plan on the basis of the equipment model and the amount of energy demand.
    Type: Application
    Filed: July 15, 2020
    Publication date: August 3, 2023
    Applicant: Mitsubishi Electric Corporation
    Inventors: Hiroyuki MORI, Hiroshi MAITANI, Yoshito NISHITA
  • Publication number: 20230243018
    Abstract: This copper alloy of one aspect contains greater than 10 mass ppm and less than 100 mass ppm of Mg, with a balance being Cu and inevitable impurities, in which among the inevitable impurities, a S amount is 10 mass ppm or less, a P amount is 10 mass ppm or less, a Se amount is 5 mass ppm or less, a Te amount is 5 mass ppm or less, an Sb amount is 5 mass ppm or less, a Bi amount is 5 mass ppm or less, an As amount is 5 mass ppm or less, a total amount of S, P, Se, Te, Sb, Bi, and As is 30 mass ppm or less, a mass ratio [Mg]/[S+P+Se+Te+Sb+Bi+As] is 0.6 to 50, an electrical conductivity is 97% IACS or greater, and a residual stress ratio at 150° C. for 1000 hours is 20% or greater.
    Type: Application
    Filed: June 30, 2021
    Publication date: August 3, 2023
    Applicant: MITSUBISHI MATERIALS CORPORATION
    Inventors: Hirotaka MATSUNAGA, Kosei FUKUOKA, Kazunari MAKI, Kenji MORIKAWA, Shinichi FUNAKI, Hiroyuki MORI
  • Publication number: 20230243020
    Abstract: A copper alloy plastically-worked material comprises Mg in the amount of greater than 10 mass ppm and 100 mass ppm or less and a balance of Cu and inevitable impurities, that comprise 10 mass ppm or less of S, 10 mass ppm or less of P, 5 mass ppm or less of Se, 5 mass ppm or less of Te, 5 mass ppm or less of Sb, 5 mass ppm or less of Bi, and 5 mass ppm or less of As. The total amount of S, P, Se, Te, Sb, Bi, and As is 30 mass ppm or less. The mass ratio of [Mg]/[S+P+Se+Te+Sb+Bi+As] is 0.6 or greater and 50 or less, the electrical conductivity is 97% IACS or greater. The tensile strength is 200 MPa or greater. The heat-resistant temperature is 150° C. or higher.
    Type: Application
    Filed: June 30, 2021
    Publication date: August 3, 2023
    Applicant: MITSUBISHI MATERIALS CORPORATION
    Inventors: Hirotaka MATSUNAGA, Yuki ITO, Kosei FUKUOKA, Kazunari MAKI, Kenji MORIKAWA, Shinichi FUNAKI, Hiroyuki MORI
  • Publication number: 20230243019
    Abstract: This copper alloy contains 10-100 mass ppm of Mg, with a balance being Cu and inevitable impurities, which comprise; 10 mass ppm or less of S, 10 mass ppm or less of P, 5 mass ppm or less of Se, 5 mass ppm or less of Te, 5 mass ppm or less of Sb, 5 mass ppm or less of Bi, 5 mass ppm or less of As. The total amount of S, P, Se, Te, Sb, Bi, and As is 30 mass ppm or less. The mass ratio [Mg]/[S+P+Se+Te+Sb+Bi+As] is 0.6 to 50. The electrical conductivity is 97% IACS or greater. The half-softening temperature is 200° C. or higher. The residual stress ratio RSG at 180° C. for 30 hours is 20% or greater. The ratio RSG/RSB at 180° C. for 30 hours is greater than 1.0.
    Type: Application
    Filed: June 30, 2021
    Publication date: August 3, 2023
    Applicant: MITSUBISHI MATERIALS CORPORATION
    Inventors: Hirotaka MATSUNAGA, Kosei FUKUOKA, Kazunari MAKI, Kenji MORIKAWA, Shinichi FUNAKI, Hiroyuki MORI
  • Publication number: 20230230219
    Abstract: This image quality evaluation device comprises: a conversion unit that converts the data of an image to two-dimensional array data of the luminance value of each pixel in the image; a processing unit that executes an averaging process, based on a plurality of filter sizes, on each pixel of the two-dimensional array data; and an evaluation unit that evaluates the quality of the image using the processing results of the processing unit.
    Type: Application
    Filed: June 2, 2020
    Publication date: July 20, 2023
    Inventor: Hiroyuki MORI
  • Patent number: 11660026
    Abstract: Embodiments are disclosed for a method for restoring a wearable biological sensor. The method includes determining that a wearable biological marker sensor comprising a reference electrode is placed within a restoration apparatus. The restoration apparatus includes a correct reference electrode, a counter electrode, and a chloride solution. The reference electrode is in electrical contact with the correct reference electrode and the counter electrode through the chloride solution. The method additionally includes determining whether the reference electrode is degraded based on a voltage differential between the reference electrode and the correct reference electrode. The method also includes restoring the reference electrode, if the reference electrode is degraded, by applying a voltage to a circuit. The circuit includes the reference electrode and the counter electrode. Further, multiple chloride ions of the chloride solution bond with a plurality of silver atoms of the reference electrode.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: May 30, 2023
    Assignee: International Business Machines Corporation
    Inventors: Keiji Matsumoto, Takahito Watanabe, Eiji Nakamura, Patrick Ruch, Hiroyuki Mori
  • Patent number: 11655523
    Abstract: This copper alloy for electronic or electric devices includes: Mg: 0.15 mass % or greater and less than 0.35 mass %; and P: 0.0005 mass % or greater and less than 0.01 mass %, with a remainder being Cu and unavoidable impurities, wherein an amount of Mg [Mg] and an amount of P [P] in terms of mass ratio satisfy [Mg]+20×[P]<0.5, and 0.20<(NFJ2/(1?NFJ3))0.5?0.45 is satisfied in a case where a proportion of J3, in which all three grain boundaries constituting a grain boundary triple junction are special grain boundaries, to total grain boundary triple junctions is represented by NFJ3, and a proportion of J2, in which two grain boundaries constituting a grain boundary triple junction are special grain boundaries and one grain boundary is a random grain boundary, to the total grain boundary triple junctions is represented by NFJ2.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: May 23, 2023
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Hirotaka Matsunaga, Kenichiro Kawasaki, Hiroyuki Mori, Kazunari Maki, Yoshiteru Akisaka
  • Patent number: 11652115
    Abstract: The present technology relates to a solid-state imaging device capable of suppressing deterioration in dark characteristics, and an electronic apparatus. The present invention is provided with: a photoelectric conversion section that performs photoelectric conversion; a charge retaining section that temporarily retains electric charge converted by the photoelectric conversion section; and a first trench formed in a semiconductor substrate between the photoelectric conversion section and the charge retaining section, the first trench being higher than the photoelectric conversion section in a depth direction of the semiconductor substrate. Alternatively, the first trench is lower than the photoelectric conversion section and higher than the charge retaining section in the depth direction of the semiconductor substrate. The present technology can be applied to, for example, a back-illuminated CMOS image sensor.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: May 16, 2023
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Tetsuya Uchida, Ryoji Suzuki, Yoshiharu Kudoh, Hiroyuki Mori, Harumi Tanaka