Patents by Inventor Hisashi Kaneko
Hisashi Kaneko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6348402Abstract: A groove or hole is formed in an insulating layer formed on a semiconductor substrate, and a first conductive layer including a first metal element is formed on a surface of the insulating layer. By oxidizing the first conductive layer, an oxide layer of the first metal element is formed on a surface of the first conductive layer. A second conductive layer including a second metal element having a free energy of oxide formation lower than that of the first metal element is deposited thereon. By reducing the oxide layer of the first metal element by the second metal element, an oxide layer of the second metal element is formed at the interface between the first conductive layer and the second conductive layer. Further, an interconnection is buried in the groove or hole of the insulating layer.Type: GrantFiled: March 16, 2000Date of Patent: February 19, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Kawanoue, Tetsuo Matsuda, Hisashi Kaneko, Tadashi Iijima
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Patent number: 6342444Abstract: A TiN film is selectively formed as a barrier layer on a Cu metal layer by selective removal of a Ti metal layer on the Si metal layer after the following steps of selectively forming a Si metal layer as an etching mask on an insulation film, forming a trench pattern by selective removal of the insulation film using the Si metal layer, forming a Cu metal layer in the trench pattern with the Si metal layer remained, forming the Ti metal layer on the Si metal layer and the Cu metal layer as a barrier material with a different kind of eutectic reaction with Cu from the reaction with the etching mask by heat-treatment in an atmosphere of nitrogen, and selectively nitriding the Ti metal layer on the Cu metal layer by heat-treatment of the Ti metal layer in an atmosphere of nitrogen.Type: GrantFiled: March 10, 2000Date of Patent: January 29, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Kazuyuki Higashi, Noriaki Matsunaga, Hiroshi Toyoda, Akihiro Kajita, Tetsuo Matsuda, Hisashi Kaneko
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Publication number: 20020003304Abstract: The semiconductor device has the first module having the first interconnection line, the second module having the second interconnection line which is shorter than the first interconnection line, the second module is formed separately from the first module, the second module is attached to the first module in a laminating direction of the first and second interconnection lines, and the second interconnection line and the first interconnection line are electrically connected to each other, and a ground line provided within the first module and paired with the first interconnection line.Type: ApplicationFiled: July 6, 2001Publication date: January 10, 2002Applicant: Kabushiki Kaisha ToshibaInventors: Noriaki Matsunaga, Hisashi Kaneko, Soichi Nadahara
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Publication number: 20020000379Abstract: In an electroplating apparatus, an electrolytic agent is filled into the portion between an anode and a dummy cathode which is opposite substantially face to face and parallel to the anode, and an electric current is supplied to this portion, thereby suppressing changes in properties of a black film during the period in which plating to a substrate to be processed is stopped. In particular, by applying an electric current to the anode immediately before plating to the substrate is resumed, the film formation characteristics of plating to the substrate can be maximally stabilized. This can reduce the consumption power and dissolution of the anode. This apparatus is particularly effective in copper plating in which the formation of a black film is significant.Type: ApplicationFiled: May 21, 2001Publication date: January 3, 2002Inventors: Tetsuo Matsuda, Hisashi Kaneko, Koji Mishima, Natsuki Makino, Junji Kunisawa
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Publication number: 20010038147Abstract: A semiconductor device manufacturing method comprises a step of forming a trench to a first insulation film formed on a semiconductor substrate, and forming a lower level wiring in the trench, a step of forming at least one conductive layer on the semiconductor substrate to coat the lower level wiring, a step of forming at least one thin film layer on the conductive layer, a step of forming a hard mask by patterning the thin film, a step of etching the conductive layer by using the hard mask as an etching mask, and forming a conductive pillar-shaped structure, whose upper surface is covered with the hard mask, on the lower level wiring, a step of forming a second insulation film on the semiconductor substrate so that the pillar-shaped structure is buried, a step of forming a wiring trench in which at least the hard mask is exposed, and a step of burying a conductor into the wiring trench after the hard mask is removed, and forming an upper level wiring in the wiring trench.Type: ApplicationFiled: July 13, 2001Publication date: November 8, 2001Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazuyuki Higashi, Noriaki Matsunaga, Akihiro Kajita, Tetsuo Matsuda, Tadashi Iijima, Hisashi Kaneko, Hideki Shibata, Naofumi Nakamura, Minakshisundaran Balasubramanian Anand, Tadashi Matsuno, Katsuya Okumura
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Publication number: 20010033894Abstract: After a thin liquid agent film is formed by supplying a liquid agent onto a plate-like developer holder, this liquid agent film and the surface of a substrate are opposed. The liquid agent film and the substrate are brought into contact with each other at a point by declining the substrate and moving it close to the liquid agent film, or by curving the substrate toward the liquid agent film. Then, the substrate is made parallel to the liquid agent film, and the liquid agent is supplied such that the contact area of the liquid agent film spreads over the entire surface by the interfacial tension between the liquid agent film and the substrate. Since a thin liquid agent film can be uniformly formed below the substrate, processing can be performed with a small consumption amount. Additionally, the liquid agent can be supplied to the substrate without holding air.Type: ApplicationFiled: March 14, 2001Publication date: October 25, 2001Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroko Nakamura, Hisashi Kaneko, Tetsuo Matsuda
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Patent number: 6306756Abstract: A method for the production of a semiconductor device having an electrode line formed in a semiconducting substrate is disclosed which comprises preparing a semiconducting substrate having trenches and/or contact holes formed preparatorily in a region destined to form the electrode line, forming a conductive film formed mainly of at least one member selected from among Cu, Ag, and Au on the surface of the semiconducting substrate, heat-treating the superposed Cu film while supplying at least an oxidizing gas thereto thereby flowing the Cu film and causing never melting to fill the trenches and/or contact holes, and removing by polishing the part of the conductive film which falls outside the region of the electrode line and completing the electrode lines consequently.Type: GrantFiled: May 26, 2000Date of Patent: October 23, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Masahiko Hasunuma, Sachiyo Ito, Keizo Shimamura, Hisashi Kaneko, Nobuo Hayasaka, Junsei Tsutsumi, Akihiro Kajita, Junichi Wada, Haruo Okano
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Publication number: 20010024691Abstract: This invention relates to a semiconductor substrate processing apparatus and method for forming interconnects by filling a circuit pattern groove and/or a hole formed in a semiconductor substrate with a plated metal film, and removing the plated metal film while leaving the metal film at the filled portion. The apparatus comprises a carry-in and carry-out section for carrying in and carrying out a semiconductor substrate, which has a circuit formed on a surface thereof, in a dry state; a plated metal film forming unit for forming a plated metal film on the semiconductor substrate which has been carried in; a bevel etching unit for etching a peripheral edge portion of the semiconductor substrate; a polishing unit for polishing at least part of the plated metal film on the semiconductor substrate; and a transport mechanism for transporting the semiconductor substrate between the above units.Type: ApplicationFiled: May 25, 2001Publication date: September 27, 2001Inventors: Norio Kimura, Koji Mishima, Junji Kunisawa, Mitsuko Odagaki, Natsuki Makino, Manabu Tsujimura, Hiroaki Inoue, Kenji Nakamura, Moriji Matsumoto, Tetsuo Matsuda, Hisashi Kaneko, Toshiyuki Morita, Nobuo Hayasaka, Katsuya Okumura
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Patent number: 6291891Abstract: A semiconductor device manufacturing method comprises a step of forming a trench to a first insulation film formed on a semiconductor substrate, and forming a lower level wiring in the trench, a step of forming at least one conductive layer on the semiconductor substrate to coat the lower level wiring, a step of forming at least one thin film layer on the conductive layer, a step of forming a hard mask by patterning the thin film, a step of etching the conductive layer by using the hard mask as an etching mask, and forming a conductive pillar-shaped structure, whose upper surface is covered with the hard mask, on the lower level wiring, a step of forming a second insulation film on the semiconductor substrate so that the pillar-shaped structure is buried, a step of forming a wiring trench in which at least the hard mask is exposed, and a step of burying a conductor into the wiring trench after the hard mask is removed, and forming an upper level wiring in the wiring trench.Type: GrantFiled: January 12, 1999Date of Patent: September 18, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Kazuyuki Higashi, Noriaki Matsunaga, Akihiro Kajita, Tetsuo Matsuda, Tadashi Iijima, Hisashi Kaneko, Hideki Shibata, Naofumi Nakamura, Minakshisundaran Balasubramanian Anand, Tadashi Matsuno, Katsuya Okumura
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Publication number: 20010013617Abstract: A method of manufacturing a semiconductor device, which comprises the steps of forming an intermediate layer on an insulating layer, forming a groove in the intermediate layer and the insulating layer, forming a first barrier layer on the intermediate layer, depositing a wiring layer on the first barrier layer to thereby fill the groove with the wiring layer, performing a flattening treatment of the wiring layer, removing a surface portion of the wiring to thereby permit the surface of the wiring to be recessed lower than a surface of the insulating layer, thus forming a recessed portion, forming a second barrier layer on the intermediate layer and on an inner wall of the recessed portion, performing a flattening treatment of the second barrier layer, thereby, and selectively removing the intermediate layer, exposing the insulating layer.Type: ApplicationFiled: January 24, 2001Publication date: August 16, 2001Applicant: Kabushiki Kaisha ToshibaInventors: Hiroshi Toyoda, Tetsuo Matsuda, Hisashi Kaneko, Hideaki Hirabayashi
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Patent number: 6229211Abstract: A semiconductor device comprises a base layer, a barrier metal layer formed on the base layer and a metal interconnect formed on the barrier metal layer, the barrier metal layer being made of at least one element &agr; selected from metal elements and at least one element &bgr; selected from a group of boron, oxygen, carbon and nitrogen and having at least two compound films &agr;&bgr;n with different compositional ratios in atomic level arranged to form a laminate. When the elements &agr; contained in the compound films &agr;&bgr;n are same and identical and at least one of the at least two compound films &agr;&bgr;n is a compound film &agr;&bgr;x (x>1), the via resistance and the interconnect resistance of the device can be reduced, while maintaining the high barrier effect.Type: GrantFiled: July 29, 1999Date of Patent: May 8, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Kawanoue, Junichi Wada, Tetsuo Matsuda, Hisashi Kaneko
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Patent number: 6150270Abstract: A method comprises forming a barrier layer for copper metallization, selectively forming a silicon film on a surface of copper wiring formed on the main surface of a semiconductor substrate, and reacting the silicon film with a non-copper metal and/or nitrogen to form a barrier layer in a self-aligned manner relative to the copper wiring. In the method, the capacitance increase in the copper wirings formed is prevented, and the barrier layer formed has a satisfactory barrier property of protecting the copper wirings.Type: GrantFiled: January 7, 1999Date of Patent: November 21, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Tetsuo Matsuda, Tadashi Iijima, Hisashi Kaneko
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Patent number: 6110647Abstract: A method of manufacturing a semiconductor device, comprises the steps of forming a first transfer pattern corresponding to a mask pattern on a major surface side of a semiconductor substrate through a first mask plate on which the first mask pattern having a straight portion and a bent portion is formed, and forming a second transfer pattern corresponding to a second mask pattern on a major surface side of the semiconductor substrate through a second mask plate on which the second mask pattern having a pattern arranged at a position corresponding to the straight portion is formed.Type: GrantFiled: February 17, 1998Date of Patent: August 29, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Soichi Inoue, Hisashi Kaneko, Masahiko Hasunuma, Takamasa Usui, Masami Aoki, Kazuko Yamamoto, Sachiko Kobayashi
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Patent number: 6090701Abstract: A method for the production of a semiconductor device having an electrode line formed in a semiconducting substrate is disclosed which comprises preparing a semiconducting substrate having trenches and/or contact holes formed preparatorily in a region destined to form the electrode line, forming a conductive film formed mainly of at least one member selected from among Cu, Ag, and Au on the surface of the semiconducting substrate, heat-treating the superposed Cu film while supplying at least an oxidizing gas thereto thereby flowing the Cu film to fill the trenches and/or contact holes, and removing by polishing the part of the conductive film which falls outside the region of the electrode line and completing the electrode lines consequently. During the heat treatment, a reducing gas is supplied in addition to the oxidizing gas to induce a local oxidation-reduction reaction and fluidify and/or flow the conductive film and consequently accomplish the embodiment of the conductive film in the trenches.Type: GrantFiled: June 20, 1995Date of Patent: July 18, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Masahiko Hasunuma, Sachiyo Ito, Keizo Shimamura, Hisashi Kaneko, Nobuo Hayasaka, Junsei Tsutsumi, Akihiro Kajita, Junichi Wada, Haruo Okano
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Patent number: 6071810Abstract: A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.Type: GrantFiled: December 23, 1997Date of Patent: June 6, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Junichi Wada, Atsuko Sakata, Tomio Katata, Takamasa Usui, Masahiko Hasunuma, Hideki Shibata, Hisashi Kaneko, Nobuo Hayasaka, Katsuya Okumura
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Patent number: 6069071Abstract: The intermetallic compound used to form a liner in the wiring of the semiconductor device is formed from a compound of a main component of the metal film used as the wiring and at least one metal material made to be dissolved in the main component to form a solid solution, or from a compound of at least two metal materials capable of forming a solid solution with the main component. The metal elements constituting the intermetallic compound are made to be dissolved in the metal film to form a solid solution during a heat treatment, and thus the barrier formed by the liner, which has been a problem studied to be solved, can be absent. Therefore, a semiconductor device excellent in resistance against electromigration and a highly reliable wiring process can be obtained.Type: GrantFiled: December 22, 1997Date of Patent: May 30, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Masahiko Hasunuma, Hisashi Kaneko
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Patent number: 6054770Abstract: An electric solid state device comprises a substrate, an amorphous thin film formed on the substrate, and a conductive thin film formed on the amorphous thin film. In this device, an interatomic distance calculated from a peak position of a halo pattern appearing in diffraction measurement of the material of the amorphous thin film is substantially equal to an interplanar space between those two adjacent specific crystal planes of the material of the conductive thin film, which are defined at least by respective atomic strings arranged in a predetermined direction in the respective planes and separated from each other by the smallest interatomic distance possible.Type: GrantFiled: August 12, 1997Date of Patent: April 25, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Toyoda, Jun-ichi Wada, Masahiko Hasunuma, Hisashi Kaneko
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Patent number: 6001461Abstract: An electronic part comprising an amorphous thin film formed on a substrate; and a metal wiring formed on the surface of the amorphous thin film; wherein an interatomic distance corresponding to a peak of halo pattern appearing in diffraction measurement of the amorphous thin film approximately matches with a spacing of a particular crystal plane defined with the first nearest interatomic distance of the metal wiring. An electronic part provided with a metal wiring formed of highly orientated crystal wherein half or more of all grain boundaries are small angle grain boundaries defined by one of grain boundaries with a relative misorientation of 10.degree. or less in tilt, rotation and combination thereof around orientation axes of neighboring crystal grains; coincidence boundaries where a .SIGMA. value is 10 or less; and grain boundaries with a relative misorientation of 3.degree. or less from the coincidence boundary.Type: GrantFiled: December 19, 1996Date of Patent: December 14, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Toyoda, Hisashi Kaneko, Masahiko Hasunuma, Takashi Kawanoue, Hiroshi Tomita, Akihiro Kajita, Masami Miyauchi, Takashi Kawakubo, Sachiyo Ito
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Patent number: 5956210Abstract: A structure for mounting at least a spring arm on at least a head arm is disclosed, which can meet the requirement for high recording density in a disk apparatus by effectively reducing the vibration of the head unit in operation. A head actuator includes at least a pair of heads mounted at the forward end of the head arm through the spring arm for reading/writing information in a discoidal recording medium. The base of the spring arm is fixedly welded to a fixing member. The head arm and the fixing member are coupled to each other by a caulking protrusion as a coupler formed on the fixing member. The overlapped portion of the head arm and the fixing member other than the coupler is formed with a vibration damping layer for preventing vibrations of one of the head arm and the fixing member from propagating to the other. This vibration damping layer is composed of a simple air gap or a vibration damping material filled in the air gap.Type: GrantFiled: October 16, 1997Date of Patent: September 21, 1999Assignee: Fujitsu LimitedInventor: Hisashi Kaneko
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Patent number: 5953634Abstract: A method of manufacturing a semiconductor device comprising the steps of, forming a diffusion-preventing thin film on a substrate, performing a first vapor deposition by supplying a source gas comprising a copper-containing organometallic compound and an oxidizing gas over the diffusion-preventing thin film thereby to allow a first conductive thin film containing copper as a main component and a trace of oxygen to be grown through a chemical vapor deposition, performing a second vapor deposition by supplying the source gas without supplying the oxidizing gas thereby to allow a second conductive thin film mainly containing copper to be grown through a chemical vapor deposition, and heat-treating the first and second conductive thin films at a temperature which is higher than those employed in the first and second vapor depositions.Type: GrantFiled: February 12, 1996Date of Patent: September 14, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Akihiro Kajita, Hisashi Kaneko