Patents by Inventor Hisashi Kaneko

Hisashi Kaneko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7238919
    Abstract: According to an aspect of the present invention, there is provided a bonding method, comprising disposing on a first body a second body with a bump interposed therebetween; and electrically and mechanically bonding the first body and the second body with the bump by passing a heating element between the first body and the second body to melt the bump by the heating element, the heating element being heated to a melting point or more of a material configuring the bump.
    Type: Grant
    Filed: February 7, 2006
    Date of Patent: July 3, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisashi Kaneko, Mie Matsuo, Hirokazu Ezawa
  • Patent number: 7232763
    Abstract: A method of manufacturing a semiconductor device includes subjecting a semiconductor wafer, which includes a copper layer formed above a semiconductor substrate and covered with an insulating film, to a dry etching using a fluorocarbon gas to partially remove the insulating film, thereby at least partially exposing a surface of the copper layer. The copper layer, the surface of which is at least partially exposed is subjected to a nitrogen plasma treatment. The semiconductor wafer having the nitrogen plasma-treated copper layer is exposed to atmosphere, and then the semiconductor wafer is subjected to a surface treatment.
    Type: Grant
    Filed: October 7, 2004
    Date of Patent: June 19, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuhiro Omura, Makiko Katano, Shoko Ito, Takaya Matsushita, Hisashi Kaneko
  • Patent number: 7214305
    Abstract: Disclosed is a method of manufacturing an electronic device, comprising forming a concave portion on the surface of a base member, forming an electrically conductive seed layer on that surface of the base member on which a plated film is to be formed, and applying an electrolytic plating treatment with the seed layer used as a common electrode under the condition that a substance for accelerating the electrolytic plating is allowed to be present in the concave portion of the base member in an amount larger than that on the surface of the base member to form a plated film.
    Type: Grant
    Filed: August 8, 2003
    Date of Patent: May 8, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuo Matsuda, Hisashi Kaneko
  • Patent number: 7202168
    Abstract: A method of producing a semiconductor device according to an aspect of the present invention comprises forming a seed film of Cu on a substrate; polycrystallizing the seed film formed on the substrate; and forming a plated film of Cu on the polycrystallized seed film by electrolytic plating.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: April 10, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Ikenoue, Hisashi Kaneko, Masaaki Hatano, Soichi Yamashita, Takashi Yoda, Makoto Sekine
  • Publication number: 20070002490
    Abstract: First and second shroud surfaces are defined along an imaginary cylinder coaxial to a recording disk. A shroud plate is located between the first and second shroud surfaces. Airflow flows outward along the surface of the rotating recording disk based on the centrifugal force. The shroud plate serves to establish the continuity of the first and second shroud surfaces. The first and second shroud surfaces and the shroud plate serve to reliably suppress turbulence of the airflow. Vibration of the recording disk is suppressed than ever. An inflow opening is located in a space between the first and second shroud surfaces. The rectifier plate is located downstream of the inflow opening. The rectifier plate serves to direct the airflow flowing along the first shroud surface to the inflow opening. A larger amount of airflow can be introduced into the inflow opening. A dust catcher receives airflow of a sufficient amount.
    Type: Application
    Filed: August 30, 2005
    Publication date: January 4, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Masaya Suwa, Hisashi Kaneko, Yoshiharu Matsuda, Keishi Shimizu
  • Publication number: 20070002495
    Abstract: A magnetic disc apparatus has a voice coil motor including a magnetic member constituting a magnetic circuit, a cover member covering the magnetic member, and a buffer member interposed between the magnetic member and the cover member. The magnetic member and the cover member are screwed with the buffer member interposed therebetween.
    Type: Application
    Filed: November 21, 2005
    Publication date: January 4, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Hiroshi Nagata, Mitsuaki Yoshida, Hisashi Kaneko, Masaya Suwa, Yoshiaki Koizumi
  • Publication number: 20060207985
    Abstract: According to an aspect of the present invention, there is provided a bonding method, comprising disposing on a first body a second body with a bump interposed therebetween; and electrically and mechanically bonding the first body and the second body with the bump by passing a heating element between the first body and the second body to melt the bump by the heating element, the heating element being heated to a melting point or more of a material configuring the bump.
    Type: Application
    Filed: February 7, 2006
    Publication date: September 21, 2006
    Inventors: Hisashi Kaneko, Mie Matsuo, Hirokazu Ezawa
  • Publication number: 20060189145
    Abstract: An insulating film formed on a conducting layer is dry-etched so as to make a connection hole in the insulating film to expose the conducting layer. Plasma is supplied onto the exposed conducting layer to dry-clean a damage layer produced in the connection hole. A product produced in the connection hole as a result of the dry cleaning is removed by a wet process. An oxide film formed in the connection hole as a result of the wet process is etched by a chemical dry process using a gas including either NF3 or HF. A thermally decomposable reaction product produced as a result of the etching is removed by heat treatment.
    Type: Application
    Filed: February 3, 2006
    Publication date: August 24, 2006
    Inventors: Makoto Honda, Kaori Yomogihara, Kazuhiro Murakami, Masanori Numano, Takahito Nagamatsu, Hideaki Harakawa, Hideto Matsuyama, Hirokazu Ezawa, Hisashi Kaneko
  • Patent number: 7091733
    Abstract: A reliability evaluation test apparatus of this invention includes a wafer storage section which stores a wafer in a state wherein the electrode pads of a number of devices formed on the wafer and the bumps of a contactor are totally in electrical contact with each other. The wafer storage section transmits/receives a test signal to/from a measurement section and has a hermetic and heat insulating structure. The wafer storage section has a pressure mechanism which presses the contactor and a heating mechanism which directly heats the wafer totally in contact with the contactor to a predetermined high temperature. The reliability of an interconnection film and insulating film formed on the semiconductor wafer are evaluated under an accelerated condition.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: August 15, 2006
    Assignees: Tokyo Electron Limited, Kabushiki Kaisha Toshiba, Ibiden Co., Ltd.
    Inventors: Kiyoshi Takekoshi, Hisatomi Hosaka, Junichi Hagihara, Kunihiko Hatsushika, Takamasa Usui, Hisashi Kaneko, Nobuo Hayasaka, Yoshiyuki Ido
  • Publication number: 20060113674
    Abstract: A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend to the bottom surface, and an insulating protective film which has an opening extended to the pad electrode layer, is provided.
    Type: Application
    Filed: January 11, 2006
    Publication date: June 1, 2006
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Toyoda, Mitsuhiro Nakao, Masahiko Hasunuma, Hisashi Kaneko, Atsuko Sakata, Toshiaki Komukai
  • Publication number: 20060102290
    Abstract: A wafer supporting plate is formed of a glass or a resin which can permeate ultraviolet rays and has a nearly disk shape. An outer diameter of the wafer supporting plate is larger than that of the semiconductor wafer which is supported. In the wafer supporting plate, a plurality of openings are formed to correspond to plural through holes of the semiconductor wafer. The opening has an open area larger than an open area of the through hole, that is, has a larger diameter.
    Type: Application
    Filed: September 9, 2005
    Publication date: May 18, 2006
    Inventors: Susumu Harada, Chiaki Takubo, Kenji Takahashi, Hideo Aoki, Hideo Numata, Hisashi Kaneko, Hirokazu Ezawa, Mie Matsuo, Hiroshi Ikenoue, Ichiro Omura
  • Publication number: 20060097399
    Abstract: A method for generating a pattern includes reading out an interconnect layout and a hole layout, the interconnect layout prescribing interconnect patterns, the hole layout prescribing hole patterns configured to connect to the interconnect patterns; extracting one of the hole patterns to be connected within the same interconnect layer level to one of the interconnect patterns in a pattern processing area; extracting a first processing area including the extracted hole pattern; calculating a first pattern density of the interconnect patterns included in the first processing area; and generating first additional patterns in the first processing area based on the first pattern density.
    Type: Application
    Filed: November 3, 2005
    Publication date: May 11, 2006
    Inventors: Masaaki Hatano, Motoya Okazaki, Junichi Wada, Takeshi Nishioka, Hisashi Kaneko, Takeshi Fujimaki, Kazuyuki Higashi, Kenji Yoshida, Noriaki Matsunaga
  • Publication number: 20060071271
    Abstract: A semiconductor device which is compact and thin in size, low in resistance of a current path and parasitic inductance and excellent in reliability is provided. This semiconductor device comprises a semiconductor substrate, a first main electrode which is formed on a front surface of the semiconductor substrate, a second main electrode which is formed on a rear surface of the semiconductor substrate, and a conducting portion which is formed in a direction to pierce through the semiconductor substrate, wherein the second main electrode is extracted to the front surface of the semiconductor substrate via the conducting portion. And, the conducting portion is a through via which has a through hole formed through the semiconductor substrate in its thickness direction and a conductive portion which is formed in the through hole and connected to the second main electrode.
    Type: Application
    Filed: September 21, 2005
    Publication date: April 6, 2006
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ichiro Omura, Kenji Takahashi, Chiaki Takubo, Hideo Aoki, Hideo Numata, Mie Matsuo, Hirokazu Ezawa, Susumu Harada, Hisashi Kaneko, Hiroshi Ikenoue, Kenichi Matsushita
  • Publication number: 20060068600
    Abstract: A method of manufacturing a semiconductor device according to an aspect of the present invention comprises forming a plated film on a substrate which has a recessed portion on its surface so as to bury in the recessed portion by a plating method; forming over the plated film a compressive stress-applying film which is composed of a material having a thermal expansion coefficient of 60% or less compared with a thermal expansion coefficient of a metal composing the plated film; heat-treating while applying a compressive stress to the plated film by the compressive stress-applying film; and removing the compressive stress-applying film and the plated film which is not buried in the recessed portion.
    Type: Application
    Filed: July 15, 2005
    Publication date: March 30, 2006
    Inventors: Hiroshi Toyoda, Sachiyo Ito, Masahiko Hasunuma, Hisashi Kaneko
  • Publication number: 20060055050
    Abstract: A semiconductor device comprises a semiconductor substrate having an through hole, a first insulation resin layer formed on an inner surface of the through hole, a second insulation resin layer formed on at least one of front and rear surfaces of the semiconductor substrate, and a first conductor layer formed in the through hole to connect at least both front and rear surfaces of the semiconductor substrate and insulated from the inner surface of the through hole with the first insulation resin layer. A second conductor layer (wiring pattern) which is electrically connected to the first conductor layer in the through hole is further provided on the second insulation resin layer. The conductor layer formed in the through hole and constituting a connecting plug has a high insulation reliability. Therefore, a semiconductor device suitable for a multi-chip package and the like can be obtained.
    Type: Application
    Filed: September 9, 2005
    Publication date: March 16, 2006
    Inventors: Hideo Numata, Hirokazu Ezawa, Chiaki Takubo, Kenji Takahashi, Hideo Aoki, Susumu Harada, Hisashi Kaneko, Hiroshi Ikenoue, Mie Matsuo, Ichiro Omura
  • Patent number: 6998342
    Abstract: An electronic device manufacturing method comprises forming an insulating film above a substrate, forming a to-be-filled region which includes at least one of an interconnection groove and a hole in the insulating film, forming a first conductive film containing a catalyst metal which accelerates electroless plating, so as to line an internal surface of the to-be-filled region, forming a second conductive film on the first conductive film by the electroless plating, so as to line the internal surface of the to-be-filled region via the first conductive film, and forming a third conductive film on the second conductive film by electroplating, so as to fill the to-be-filled region via the first conductive film and the second conductive film.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: February 14, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuo Matsuda, Hiroshi Toyoda, Hisashi Kaneko
  • Publication number: 20060024952
    Abstract: A method of producing a semiconductor device according to an aspect of the present invention comprises forming a seed film of Cu on a substrate; polycrystallizing the seed film formed on the substrate; and forming a plated film of Cu on the polycrystallized seed film by electrolytic plating.
    Type: Application
    Filed: May 25, 2005
    Publication date: February 2, 2006
    Inventors: Hiroshi Ikenoue, Hisashi Kaneko, Masaaki Hatano, Soichi Yamashita, Takashi Yoda, Makoto Sekine
  • Patent number: 6992864
    Abstract: A thermal component is mounted on the front surface of an isolator sheet within a first specific area. A thermally-conductive material is located on the back surface of the isolator sheet on the back of the first specific area. An electrically-conductive material is located on the front surface of the isolator sheet within a second specific area. A thermally-insulating material is located on the back surface of the isolator sheet on the back of the second specific area. The flexible printed circuit board unit of this type allows heat of the thermal component to efficiently radiate from the thermally-conductive material. An increase in temperature can be suppressed in the thermal component. Heat can reliably stay in the electrically-conductive material when a solder material is applied to the surface of the electrically-conductive material. The solder material is allowed to reliably fuse.
    Type: Grant
    Filed: January 21, 2004
    Date of Patent: January 31, 2006
    Assignee: Fujitsu Limited
    Inventors: Hisashi Kaneko, Hiroyuki Iwahara, Yukihiro Komura, Mitsuhiro Izumi, Shinji Fujimoto
  • Publication number: 20050253575
    Abstract: A reliability evaluation test apparatus of this invention includes a wafer storage section which stores a wafer in a state wherein the electrode pads of a number of devices formed on the wafer and the bumps of a contactor are totally in electrical contact with each other. The wafer storage section transmits/receives a test signal to/from a measurement section and has a hermetic and heat insulating structure. The wafer storage section has a pressure mechanism which presses the contactor and a heating mechanism which directly heats the wafer totally in contact with the contactor to a predetermined high temperature. The reliability of an interconnection film and insulating film formed on the semiconductor wafer are evaluated under an accelerated condition.
    Type: Application
    Filed: July 13, 2005
    Publication date: November 17, 2005
    Inventors: Kiyoshi Takekoshi, Hisatomi Hosaka, Junichi Hagihara, Kunihiko Hatsushika, Takamasa Usui, Hisashi Kaneko, Nobuo Hayasaka, Yoshiyuki Ido
  • Publication number: 20050241955
    Abstract: A substrate processing apparatus and a substrate processing method can appropriately control the charge of a substrate depending on the type of wet processing, thereby reducing defective processing due to static electricity on the surface of the substrate. The substrate processing apparatus includes: a static electricity adjustment section for adjusting static electricity on a substrate; and a wet processing apparatus for carrying out wet processing of the static electricity-adjusted substrate. The static electricity adjustment section removes static electricity from the substrate or charges the substrate into a desired charged state, for example.
    Type: Application
    Filed: April 22, 2005
    Publication date: November 3, 2005
    Inventors: Koji Mishima, Hidenao Suzuki, Kazufumi Nomura, Hisashi Kaneko, Hiroshi Toyoda