Abstract: A semiconductor device manufacturing method of the this invention having the step of forming an interlayer insulating film on a semiconductor substrate, the step of making interconnection groove in the interlayer insulating film, the step of filling the inside of the interconnection groove with a conductive film which is made of a first substance and is thicker than the depth of the interconnection groove, the step of thermally stabilizing the size of crystal grains in an Al film either at the same time or after the Al film has been formed, the step of forming a Cu film on the Al film, the step of selectively forming &thgr; phase layers in a crystal grain boundary of the Al film by causing Cu to selectively diffuse into the crystal grain boundary of Al film and of allowing the &thgr; phase layers to divide the Al film in the interconnection groove into fine Al interconnections shorter than the Blech critical length, and the step of removing the Al film and Cu film outside the interconnection groove.

Abstract: A thickness measuring system comprises: an eddy current loss measuring sensor having an exciting coil for receiving a high frequency current to excite a high frequency magnetic field to excite an eddy current in a conductive film, and a receiving coil for outputting the high frequency current which is influenced by an eddy current loss caused by the eddy current; an impedance analyzer for measuring the variation in impedance of the eddy current loss measuring sensor, the variation in current value of the high frequency current or the variation in phase of the high frequency current on the basis of the high frequency current outputted from the receiving coil; an optical displacement sensor for measuring the distance between the conductive film and the eddy current loss measuring sensor; and a control computer including a thickness calculating part for calculating the thickness of the conductive film on the basis of various measured results of the impedance analyzer and optical displacement sensor, and the eddy

Abstract: A semiconductor device is formed by a compound film &agr;&ggr;x made of at least one element &agr; selected from metal elements and at least one element &ggr; selected from the group consisting of boron, carbon, and nitrogen on a base layer containing oxygen (O), and forming a compound film &agr;&ggr;yOz by causing the compound film &agr;&ggr;x to reduce the base layer and thereby oxidizing the compound film &agr;&ggr;x on an interface of the compound film &agr;&ggr;x and the base layer, wherein each of x and y is a ratio of the number of atoms of the element &ggr; to the number of atoms of the element &agr;, and z is a ratio of the number of atoms of the oxygen to the number of atoms of the element &agr;.

Abstract: The present invention provides an electroless plating liquid which allows a plating rate to be controlled, is not largely influential on semiconductor characteristics, and poses no problem on the health of workers, and a method of forming an interconnection according to a electroless plating process which uses such an electroless plating liquid. The electroless copper plating liquid contains dihydric copper ions, a complexing agent, an aldehyde acid, and an organic alkali. The electroless copper plating liquid is preferably be used in a method having the steps of forming an auxiliary seed layer for reinforcing a copper seed layer in an interconnection groove defined in a surface of a semiconductor device, and performing an electrolytic plating process using the seed layer including the auxiliary seed layer as a current feeding layer, for thereby filling copper in the interconnection groove defined in the surface of the semiconductor device.

Abstract: A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.

Abstract: A semiconductor device manufacturing method of the this invention having the step of forming an interlayer insulating film on a semiconductor substrate, the step of making interconnection groove in the interlayer insulating film, the step of filling the inside of the interconnection groove with a conductive film which is made of a first substance and is thicker than the depth of the interconnection groove, the step of thermally stabilizing the size of crystal grains in an Al film either at the same time or after the Al film has been formed, the step of forming a Cu film on the Al film, the step of selectively forming &thgr; phase layers in a crystal grain boundary of the Al film by causing Cu to selectively diffuse into the crystal grain boundary of Al film and of allowing the &thgr; phase layers to divide the Al film in the interconnection groove into fine Al interconnections shorter than the Blech critical length, and the step of removing the Al film and Cu film outside the interconnection groove.

Abstract: A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend to the bottom surface, and an insulating protective film which has an opening extended to the pad electrode layer, is provided.

Abstract: A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.

Abstract: A method for manufacturing a semiconductor device, comprising controlling a humidity in an atmosphere around a low dielectric constant insulating film at 30% or less, during a processing period and a transfer period between processing equipments, in which at least a part of said low dielectric constant insulating film is exposed to the atmosphere.

Abstract: A cathode potential is applied to a conductive layer formed on a substrate having a depression pattern. A plating solution in electrical contact with an anode is supplied to the conductive layer to form a plating film on the conductive layer. At this time, the plating solution is supplied by causing an impregnated member containing the plating solution to face the conductive layer. Since the plating solution stays in the depression, a larger amount of plating solution is supplied than on the upper surface of the substrate, and the plating rate of the plating film in the depression increases. Consequently, the plating film can be preferentially formed in the depression such as a groove or hole.

Abstract: Disclosed is a semiconductor device, comprising a semiconductor substrate, an insulating layer and a metallic wiring layer formed on the semiconductor substrate; and an intermediate layer formed between the insulating layer and the metallic wiring layer in contact with both the insulating layer and the metallic wiring layer, wherein the intermediate layer contains the metallic material forming the metallic wiring layer, Si and O.

Abstract: A semiconductor device manufacturing method of the this invention having the step of forming an interlayer insulating film on a semiconductor substrate, the step of making interconnection groove in the interlayer insulating film, the step of filling the inside of the interconnection groove with a conductive film which is made of a first substance and is thicker than the depth of the interconnection groove, the step of thermally stabilizing the size of crystal grains in an Al film either at the same time or after the Al film has been formed, the step of forming a Cu film on the Al film, the step of selectively forming &thgr; phase layers in a crystal grain boundary of the Al film by causing Cu to selectively diffuse into the crystal grain boundary of Al film and of allowing the &thgr; phase layers to divide the Al film in the interconnection groove into fine Al interconnections shorter than the Blech critical length, and the step of removing the Al film and Cu film outside the interconnection groove.

Abstract: A film formation method for manufacture of a semiconductor device includes the steps of forming a first metal film as a continuous film on a substrate, forming a second metal film as discontinuous films on the substrate formed with the first metal film, and forming a third metal film by plating on the substrate formed with the first and second metal films.

Abstract: The present invention relates to a plating method and a plating apparatus which can attain embedding of copper into fine interconnection patterns with the use of a plating liquid having high throwing power and leveling properties, and which can make the film thickness of the plated film substantially equal between the interconnection region and the non-interconnection region, thereby facilitating a later CMP processing. A plating method comprising filling a plating liquid containing metal ions and an additive into a plating space formed between a substrate and an anode disposed closely to the substrate so as to face the substrate, and changing the concentration of the additive in the plating liquid filled into the plating space during a plating process.

Abstract: An electronic device manufacturing method comprises forming an insulating film above a substrate, forming a to-be-filled region which includes at least one of an interconnection groove and a hole in the insulating film, forming a first conductive film containing a catalyst metal which accelerates electroless plating, so as to line an internal surface of the to-be-filled region, forming a second conductive film on the first conductive film by the electroless plating, so as to line the internal surface of the to-be-filled region via the first conductive film, and forming a third conductive film on the second conductive film by electroplating, so as to fill the to-be-filled region via the first conductive film and the second conductive film.

Abstract: A cathode potential is applied to a conductive layer formed on a substrate having a depression pattern. A plating solution in electrical contact with an anode is supplied to the conductive layer to form a plating film on the conductive layer. At this time, the plating solution is supplied by causing an impregnated member containing the plating solution to face the conductive layer. Since the plating solution stays in the depression, a larger amount of plating solution is supplied than on the upper surface of the substrate, and the plating rate of the plating film in the depression increases. Consequently, the plating film can be preferentially formed in the depression such as a groove or hole.

Abstract: A semiconductor device manufacturing method comprises a step of forming a trench to a first insulation film formed on a semiconductor substrate, and forming a lower level wiring in the trench, a step of forming at least one conductive layer on the semiconductor substrate to coat the lower level wiring, a step of forming at least one thin film layer on the conductive layer, a step of forming a hard mask by patterning the thin film, a step of etching the conductive layer by using the hard mask as an etching mask, and forming a conductive pillar-shaped structure, whose upper surface is covered with the hard mask, on the lower level wiring, a step of forming a second insulation film on the semiconductor substrate so that the pillar-shaped structure is buried, a step of forming a wiring trench in which at least the hard mask is exposed, and a step of burying a conductor into the wiring trench after the hard mask is removed, and forming an upper level wiring in the wiring trench.

Abstract: A method for manufacturing a semiconductor device, comprising controlling a humidity in an atmosphere around a low dielectric constant insulating film at 30% or less, during a processing period and a transfer period between processing equipments, in which at least a part of said low dielectric constant insulating film is exposed to the atmosphere

Abstract: A substrate is plated with a metal film of uniform thickness only in a limited area thereof which is to be plated. A substrate plating apparatus has a substrate holder for holding a substrate and a plating cell for plating a portion of a surface, to be plated, of the substrate held by the substrate holder. The plating cell has an anode disposed so as to cover the portion of the surface, to be plated, of the substrate held by the substrate holder, a cathode for supplying a current to the surface, to be plated, of the substrate in such a state that the cathode is brought into contact with the substrate, a plating liquid supplying device for supplying a plating liquid between the anode and the surface, to be plated, of the substrate, and a power source for applying a voltage between the anode and the cathode.

Abstract: This invention relates, particularly, to a plating method and apparatus for a substrate for uses, such as the filling of a metal, e.g., copper (Cu), into a fine interconnection pattern (recesses) formed in a semiconductor substrate.