Patents by Inventor Hisashi Kaneko

Hisashi Kaneko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6746589
    Abstract: The present invention relates to a plating method and a plating apparatus which can attain embedding of copper into fine interconnection patterns with use of a plating liquid having high throwing power and leveling properties, and which can make film thickness of a plated film substantially equal between an interconnection region and a non-interconnection region. A plating method comprises filling a plating liquid containing metal ions and an additive into a plating space formed between a substrate and an anode disposed closely to the substrate so as to face the substrate, and changing concentration of the additive in the plating liquid filled into the plating space during a plating process.
    Type: Grant
    Filed: September 19, 2001
    Date of Patent: June 8, 2004
    Assignees: Ebara Corporation, Kabushiki Kaisha Toshiba
    Inventors: Koji Mishima, Hiroaki Inoue, Natsuki Makino, Junji Kunisawa, Kenji Nakamura, Tetsuo Matsuda, Hisashi Kaneko, Toshiyuki Morita
  • Publication number: 20040104482
    Abstract: One via contact through which upper and lower interconnections of a multilevel interconnection are connected to each other is provided when the width or volume of the lower interconnection is not larger than a given value. A plurality of via contacts are arranged at regular intervals, each of which is not larger than a given value, in an effective diffusion region of voids included in the lower interconnection, when the width or volume of the lower interconnection exceeds a given value.
    Type: Application
    Filed: November 21, 2003
    Publication date: June 3, 2004
    Inventors: Koji Miyamoto, Kenji Yoshida, Hisashi Kaneko
  • Patent number: 6727593
    Abstract: A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend to the bottom surface, and an insulating protective film which has an opening extended to the pad electrode layer, is provided.
    Type: Grant
    Filed: February 28, 2002
    Date of Patent: April 27, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Toyoda, Mitsuhiro Nakao, Masahiko Hasunuma, Hisashi Kaneko, Atsuko Sakata, Toshiaki Komukai
  • Publication number: 20040069646
    Abstract: A plating method and apparatus for a substrate fills a metal, e.g., copper, into a fine interconnection pattern formed in a semiconductor substrate. The apparatus has a substrate holding portion 36 horizontally holding and rotating a substrate with its surface to be plated facing upward. A seal material 90 contacts a peripheral edge portion of the surface, sealing the in a watertight manner. A cathode electrode 88 passes an electric current upon contact with the substrate. A cathode portion 38 rotates integrally with the substrate holding portion 36. An electrode arm portion 30 is above the cathode portion 38 and movable horizontally and vertically and has an anode 98 face-down. Plating liquid is poured into a space between the surface to be plated and the anode 98 brought close to the surface to be plated. Thus, plating treatment and treatments incidental thereto can be performed by a single unit.
    Type: Application
    Filed: August 1, 2003
    Publication date: April 15, 2004
    Inventors: Junji Kunisawa, Mitsuko Odagaki, Natsuki Makino, Koji Mishima, Kenji Nakamura, Hiroaki Inoue, Norio Kimura, Tetsuo Matsuda, Hisashi Kaneko, Nobuo Hayasaka, Katsuya Okumura, Manabu Tsujimura, Toshiyuki Morita
  • Publication number: 20040050711
    Abstract: The present invention relates to a method and apparatus for separating out metal copper according to an electroplating of copper using, for example, a solution of copper sulfate to produce copper interconnections on a surface of a substrate. The substrate is brought into contact, at least once, with a processing solution containing at least one of organic substance and sulfur compound which are contained in a plating solution. Thereafter, the substrate is brought into contact with the plating solution to plate the substrate.
    Type: Application
    Filed: September 12, 2003
    Publication date: March 18, 2004
    Inventors: Koji Mishima, Mizuki Nagai, Ryoichi Kimizuka, Tetsuo Matsuda, Hisashi Kaneko
  • Publication number: 20040043602
    Abstract: A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.
    Type: Application
    Filed: August 29, 2003
    Publication date: March 4, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Junichi Wada, Atsuko Sakata, Tomio Katata, Takamasa Usui, Masahiko Hasunuma, Hideki Shibata, Hisashi Kaneko, Nobuo Hayasaka, Katsuya Okumura
  • Publication number: 20040012091
    Abstract: One via contact through which upper and lower interconnections of a multilevel interconnection are connected to each other is provided when the width or volume of the lower interconnection is not larger than a given value. A plurality of via contacts are arranged at regular intervals, each of which is not larger than a given value, in an effective diffusion region of voids included in the lower interconnection, when the width or volume of the lower interconnection exceeds a given value.
    Type: Application
    Filed: January 7, 2003
    Publication date: January 22, 2004
    Inventors: Koji Miyamoto, Kenji Yoshida, Hisashi Kaneko
  • Patent number: 6678112
    Abstract: A magnetic or other disk drive device includes a base having an opening through which electrical signal lines in a cable pass. The signal lines are preferably in a flexible printed circuit (FPC). The opening is sealed by adhesively securing a cover to the base around the periphery of the opening, either directly or indirectly. In one embodiment, the cover is secured directly to the base, except of course where it crosses signal lines, while in other embodiments the FPC is secured directly to the base and the cover is secured to the FPC. In the latter embodiments, a portion of the FPC extends around the periphery of the opening, and the signal lines pass through the opening. Double sided adhesive tape may be used to secure the FPC to the base, if desired.
    Type: Grant
    Filed: January 24, 2000
    Date of Patent: January 13, 2004
    Assignee: Fujitsu Limited
    Inventor: Hisashi Kaneko
  • Publication number: 20040005774
    Abstract: A method of forming a cap film comprises a first polishing step of performing a polishing operation at selectivity of R1 (=removal rate for the cap film/removal rate for the insulating film), and a second polishing step of performing a polishing operation at selectivity of R2 (=removal rate for the cap film/removal rate for the insulating film). Each of the polishing operations is performed by using a slurry having the condition of R1>R2. By performing the polishing operations at different selectivity, the cap film free from problems such as dishing of the cap film and the residual cap film on side walls of a recess is formed. Consequently, a semiconductor device having an excellent RC characteristic can be provided.
    Type: Application
    Filed: June 23, 2003
    Publication date: January 8, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Toyoda, Hiroyuki Yano, Gaku Minamihaba, Dai Fukushima, Tetsuo Matsuda, Hisashi Kaneko
  • Patent number: 6673704
    Abstract: A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.
    Type: Grant
    Filed: July 8, 2002
    Date of Patent: January 6, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junichi Wada, Atsuko Sakata, Tomio Katata, Takamasa Usui, Masahiko Hasunuma, Hideki Shibata, Hisashi Kaneko, Nobuo Hayasaka, Katsuya Okumura
  • Patent number: 6670714
    Abstract: One via contact through which upper and lower interconnections of a multilevel interconnection are connected to each other is provided when the width or volume of the lower interconnection is not larger than a given value. A plurality of via contacts are arranged at regular intervals, each of which is not larger than a given value, in an effective diffusion region of voids included in the lower interconnection, when the width or volume of the lower interconnection exceeds a given value.
    Type: Grant
    Filed: January 7, 2003
    Date of Patent: December 30, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Miyamoto, Kenji Yoshida, Hisashi Kaneko
  • Publication number: 20030214010
    Abstract: A method of manufacturing a semiconductor device, which comprises the steps of forming an intermediate layer on an insulating layer, forming a groove in the intermediate layer and the insulating layer, forming a first barrier layer on the intermediate layer, depositing a wiring layer on the first barrier layer to thereby fill the groove with the wiring layer, performing a flattening treatment of the wiring layer, removing a surface portion of the wiring to thereby permit the surface of the wiring to be recessed lower than a surface of the insulating layer, thus forming a recessed portion, forming a second barrier layer on the intermediate layer and on an inner wall of the recessed portion, performing a flattening treatment of the second barrier layer, thereby, and selectively removing the intermediate layer, exposing the insulating layer.
    Type: Application
    Filed: April 29, 2003
    Publication date: November 20, 2003
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Toyoda, Tetsuo Matsuda, Hisashi Kaneko, Hideaki Hirabayashi
  • Patent number: 6638411
    Abstract: The present invention relates to a method and apparatus for separating out metal copper according to an electroplating of copper using, for example, a solution of copper sulfate to produce copper interconnections on a surface of a substrate. The substrate is brought into contact, at least once, with a processing solution containing at least one of organic substance and sulfur compound which are contained in a plating solution. Thereafter, the substrate is brought into contact with the plating solution to plate the substrate.
    Type: Grant
    Filed: January 27, 2000
    Date of Patent: October 28, 2003
    Assignees: Ebara Corporation, Kabushiki Kaisha Toshiba
    Inventors: Koji Mishima, Mizuki Nagai, Ryoichi Kimizuka, Tetsuo Matsuda, Hisashi Kaneko
  • Patent number: 6632335
    Abstract: A plating method and apparatus for a substrate fills a metal, e.g., copper, into a fine interconnection pattern formed in a semiconductor substrate. The apparatus has a substrate holding portion 36 horizontally holding and rotating a substrate with its surface to be plated facing upward. A seal material 90 contacts a peripheral edge portion of the surface, sealing the portion in a watertight manner. A cathode electrode 88 passes an electric current upon contact with the substrate. A cathode portion 38 rotates integrally with the substrate holding portion 36. An electrode arm portion 30 is above the cathode portion 38 and movable horizontally and vertically and has an anode 98 face-down. Plating liquid is poured into a space between the surface to be plated and the anode 98 brought close to the surface to be plated. Thus, plating treatment and treatments incidental thereto can be performed by a single unit.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: October 14, 2003
    Assignees: Ebara Corporation, Kabushiki Kaisha Toshiba
    Inventors: Junji Kunisawa, Mitsuko Odagaki, Natsuki Makino, Koji Mishima, Kenji Nakamura, Hiroaki Inoue, Norio Kimura, Tetsuo Matsuda, Hisashi Kaneko, Nobuo Hayasaka, Katsuya Okumura, Manabu Tsujimura, Toshiyuki Morita
  • Patent number: 6632476
    Abstract: After a thin liquid agent film is formed by supplying a liquid agent onto a plate-like developer holder, this liquid agent film and the surface of a substrate are opposed. The liquid agent film and the substrate are brought into contact with each other at a point by declining the substrate and moving it close to the liquid agent film, or by curving the substrate toward the liquid agent film. Then, the substrate is made parallel to the liquid agent film, and the liquid agent is supplied such that the contact area of the liquid agent film spreads over the entire surface by the interfacial tension between the liquid agent film and the substrate. Since a thin liquid agent film can be uniformly formed below the substrate, processing can be performed with a small consumption amount. Additionally, the liquid agent can be supplied to the substrate without holding air.
    Type: Grant
    Filed: March 14, 2001
    Date of Patent: October 14, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroko Nakamura, Hisashi Kaneko, Tetsuo Matsuda
  • Patent number: 6633450
    Abstract: A method and an apparatus for controlling a disk drive are contrived to reduce consumed electric power of a spindle motor of the disk drive while an operation continues. The disk drive has a disk storage medium, the spindle motor for rotating the disk storage medium, and a head for reading data on the disk storage medium. This control method comprises a first step of detecting a load of the spindle motor or a load capacity of a power source of the disk drive, and a second step of selecting any one of a first mode of revolving the spindle motor at a comparatively high speed and reading the data on the disk storage medium by the head, and a second mode of revolving the spindle motor at a comparatively low speed and reading the data on the disk storage medium by the head in accordance with a detected result of the first step.
    Type: Grant
    Filed: August 10, 1999
    Date of Patent: October 14, 2003
    Assignee: Fujitsu Limited
    Inventor: Hisashi Kaneko
  • Patent number: 6611060
    Abstract: A method of forming a cap film comprises a first polishing step of performing a polishing operation at selectivity of R1 (=removal rate for the cap film/removal rate for the insulating film), and a second polishing step of performing a polishing operation at selectivity of R2 (=removal rate for the cap film/removal rate for the insulating film). Each of the polishing operations is performed by using a slurry having the condition of R1>R2. By performing the polishing operations at different selectivity, the cap film free from problems such as dishing of the cap film and the residual cap film on side walls of a recess is formed. Consequently, a semiconductor device having an excellent RC characteristic can be provided.
    Type: Grant
    Filed: October 3, 2000
    Date of Patent: August 26, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Toyoda, Hiroyuki Yano, Gaku Minamihaba, Dai Fukushima, Tetsuo Matsuda, Hisashi Kaneko
  • Patent number: 6579785
    Abstract: A method of manufacturing a semiconductor device, which comprises the steps of forming an intermediate layer on an insulating layer, forming a groove in the intermediate layer and the insulating layer, forming a first barrier layer on the intermediate layer, depositing a wiring layer on the first barrier layer to thereby fill the groove with the wiring layer, performing a flattening treatment of the wiring layer, removing a surface portion of the wiring to thereby permit the surface of the wiring to be recessed lower than a surface of the insulating layer, thus forming a recessed portion, forming a second barrier layer on the intermediate layer and on an inner wall of the recessed portion, performing a flattening treatment of the second barrier layer, thereby, and selectively removing the intermediate layer, exposing the insulating layer.
    Type: Grant
    Filed: January 24, 2001
    Date of Patent: June 17, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Toyoda, Tetsuo Matsuda, Hisashi Kaneko, Hideaki Hirabayashi
  • Patent number: 6563308
    Abstract: A thickness measuring system comprises: an eddy current loss measuring sensor having an exciting coil for receiving a high frequency current to excite a high frequency magnetic field to excite an eddy current in a conductive film, and a receiving coil for outputting the high frequency current which is influenced by an eddy current loss caused by the eddy current; an impedance analyzer for measuring the variation in impedance of the eddy current loss measuring sensor, the variation in current value of the high frequency current or the variation in phase of the high frequency current on the basis of the high frequency current outputted from the receiving coil; an optical displacement sensor for measuring the distance between the conductive film and the eddy current loss measuring sensor; and a control computer including a thickness calculating part for calculating the thickness of the conductive film on the basis of various measured results of the impedance analyzer and optical displacement sensor, and the eddy
    Type: Grant
    Filed: March 27, 2001
    Date of Patent: May 13, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Osamu Nagano, Yuichiro Yamazaki, Motosuke Miyoshi, Hisashi Kaneko, Tetsuo Matsuda
  • Patent number: 6555925
    Abstract: The present invention is a method of producing a semiconductor device in which at least one alignment mark to be used in an exposure process of a lithographic process is formed of a wiring material which is copper or includes copper as a main component, and the alignment mark is formed entirely in an area outside an area where dicing is to be executed.
    Type: Grant
    Filed: March 2, 2000
    Date of Patent: April 29, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuyuki Higashi, Noriaki Matsunaga, Akihiro Kajita, Tamao Takase, Hisashi Kaneko, Hideki Shibata