Patents by Inventor Hisashi Kaneko
Hisashi Kaneko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6767437Abstract: In an electroplating apparatus, an electrolytic agent is filled into the portion between an anode and a dummy cathode which is opposite substantially face to face and parallel to the anode, and an electric current is supplied to this portion, thereby suppressing changes in properties of a black film during the period in which plating to a substrate to be processed is stopped. In particular, by applying an electric current to the anode immediately before plating to the substrate is resumed, the film formation characteristics of plating to the substrate can be maximally stabilized. This can reduce the consumption power and dissolution of the anode. This apparatus is particularly effective in copper plating in which the formation of a black film is significant.Type: GrantFiled: May 21, 2001Date of Patent: July 27, 2004Assignees: Kabushiki Kaisha Toshiba, Ebara CorporationInventors: Tetsuo Matsuda, Hisashi Kaneko, Koji Mishima, Natsuki Makino, Junji Kunisawa
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Patent number: 6764585Abstract: An electronic device manufacturing method comprises forming an insulating film above a substrate, forming a to-be-filled region which includes at least one of an interconnection groove and a hole in the insulating film, forming a first conductive film containing a catalyst metal which accelerates electroless plating, so as to line an internal surface of the to-be-filled region, forming a second conductive film on the first conductive film by the electroless plating, so as to line the internal surface of the to-be-filled region via the first conductive film, and forming a third conductive film on the second conductive film by electroplating, so as to fill the to-be-filled region via the first conductive film and the second conductive film.Type: GrantFiled: November 1, 2001Date of Patent: July 20, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Tetsuo Matsuda, Hiroshi Toyoda, Hisashi Kaneko
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Patent number: 6746589Abstract: The present invention relates to a plating method and a plating apparatus which can attain embedding of copper into fine interconnection patterns with use of a plating liquid having high throwing power and leveling properties, and which can make film thickness of a plated film substantially equal between an interconnection region and a non-interconnection region. A plating method comprises filling a plating liquid containing metal ions and an additive into a plating space formed between a substrate and an anode disposed closely to the substrate so as to face the substrate, and changing concentration of the additive in the plating liquid filled into the plating space during a plating process.Type: GrantFiled: September 19, 2001Date of Patent: June 8, 2004Assignees: Ebara Corporation, Kabushiki Kaisha ToshibaInventors: Koji Mishima, Hiroaki Inoue, Natsuki Makino, Junji Kunisawa, Kenji Nakamura, Tetsuo Matsuda, Hisashi Kaneko, Toshiyuki Morita
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Publication number: 20040104482Abstract: One via contact through which upper and lower interconnections of a multilevel interconnection are connected to each other is provided when the width or volume of the lower interconnection is not larger than a given value. A plurality of via contacts are arranged at regular intervals, each of which is not larger than a given value, in an effective diffusion region of voids included in the lower interconnection, when the width or volume of the lower interconnection exceeds a given value.Type: ApplicationFiled: November 21, 2003Publication date: June 3, 2004Inventors: Koji Miyamoto, Kenji Yoshida, Hisashi Kaneko
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Patent number: 6727593Abstract: A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend to the bottom surface, and an insulating protective film which has an opening extended to the pad electrode layer, is provided.Type: GrantFiled: February 28, 2002Date of Patent: April 27, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Toyoda, Mitsuhiro Nakao, Masahiko Hasunuma, Hisashi Kaneko, Atsuko Sakata, Toshiaki Komukai
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Publication number: 20040069646Abstract: A plating method and apparatus for a substrate fills a metal, e.g., copper, into a fine interconnection pattern formed in a semiconductor substrate. The apparatus has a substrate holding portion 36 horizontally holding and rotating a substrate with its surface to be plated facing upward. A seal material 90 contacts a peripheral edge portion of the surface, sealing the in a watertight manner. A cathode electrode 88 passes an electric current upon contact with the substrate. A cathode portion 38 rotates integrally with the substrate holding portion 36. An electrode arm portion 30 is above the cathode portion 38 and movable horizontally and vertically and has an anode 98 face-down. Plating liquid is poured into a space between the surface to be plated and the anode 98 brought close to the surface to be plated. Thus, plating treatment and treatments incidental thereto can be performed by a single unit.Type: ApplicationFiled: August 1, 2003Publication date: April 15, 2004Inventors: Junji Kunisawa, Mitsuko Odagaki, Natsuki Makino, Koji Mishima, Kenji Nakamura, Hiroaki Inoue, Norio Kimura, Tetsuo Matsuda, Hisashi Kaneko, Nobuo Hayasaka, Katsuya Okumura, Manabu Tsujimura, Toshiyuki Morita
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Publication number: 20040050711Abstract: The present invention relates to a method and apparatus for separating out metal copper according to an electroplating of copper using, for example, a solution of copper sulfate to produce copper interconnections on a surface of a substrate. The substrate is brought into contact, at least once, with a processing solution containing at least one of organic substance and sulfur compound which are contained in a plating solution. Thereafter, the substrate is brought into contact with the plating solution to plate the substrate.Type: ApplicationFiled: September 12, 2003Publication date: March 18, 2004Inventors: Koji Mishima, Mizuki Nagai, Ryoichi Kimizuka, Tetsuo Matsuda, Hisashi Kaneko
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Publication number: 20040043602Abstract: A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.Type: ApplicationFiled: August 29, 2003Publication date: March 4, 2004Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Junichi Wada, Atsuko Sakata, Tomio Katata, Takamasa Usui, Masahiko Hasunuma, Hideki Shibata, Hisashi Kaneko, Nobuo Hayasaka, Katsuya Okumura
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Publication number: 20040012091Abstract: One via contact through which upper and lower interconnections of a multilevel interconnection are connected to each other is provided when the width or volume of the lower interconnection is not larger than a given value. A plurality of via contacts are arranged at regular intervals, each of which is not larger than a given value, in an effective diffusion region of voids included in the lower interconnection, when the width or volume of the lower interconnection exceeds a given value.Type: ApplicationFiled: January 7, 2003Publication date: January 22, 2004Inventors: Koji Miyamoto, Kenji Yoshida, Hisashi Kaneko
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Patent number: 6678112Abstract: A magnetic or other disk drive device includes a base having an opening through which electrical signal lines in a cable pass. The signal lines are preferably in a flexible printed circuit (FPC). The opening is sealed by adhesively securing a cover to the base around the periphery of the opening, either directly or indirectly. In one embodiment, the cover is secured directly to the base, except of course where it crosses signal lines, while in other embodiments the FPC is secured directly to the base and the cover is secured to the FPC. In the latter embodiments, a portion of the FPC extends around the periphery of the opening, and the signal lines pass through the opening. Double sided adhesive tape may be used to secure the FPC to the base, if desired.Type: GrantFiled: January 24, 2000Date of Patent: January 13, 2004Assignee: Fujitsu LimitedInventor: Hisashi Kaneko
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Publication number: 20040005774Abstract: A method of forming a cap film comprises a first polishing step of performing a polishing operation at selectivity of R1 (=removal rate for the cap film/removal rate for the insulating film), and a second polishing step of performing a polishing operation at selectivity of R2 (=removal rate for the cap film/removal rate for the insulating film). Each of the polishing operations is performed by using a slurry having the condition of R1>R2. By performing the polishing operations at different selectivity, the cap film free from problems such as dishing of the cap film and the residual cap film on side walls of a recess is formed. Consequently, a semiconductor device having an excellent RC characteristic can be provided.Type: ApplicationFiled: June 23, 2003Publication date: January 8, 2004Applicant: Kabushiki Kaisha ToshibaInventors: Hiroshi Toyoda, Hiroyuki Yano, Gaku Minamihaba, Dai Fukushima, Tetsuo Matsuda, Hisashi Kaneko
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Patent number: 6673704Abstract: A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.Type: GrantFiled: July 8, 2002Date of Patent: January 6, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Junichi Wada, Atsuko Sakata, Tomio Katata, Takamasa Usui, Masahiko Hasunuma, Hideki Shibata, Hisashi Kaneko, Nobuo Hayasaka, Katsuya Okumura
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Patent number: 6670714Abstract: One via contact through which upper and lower interconnections of a multilevel interconnection are connected to each other is provided when the width or volume of the lower interconnection is not larger than a given value. A plurality of via contacts are arranged at regular intervals, each of which is not larger than a given value, in an effective diffusion region of voids included in the lower interconnection, when the width or volume of the lower interconnection exceeds a given value.Type: GrantFiled: January 7, 2003Date of Patent: December 30, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Koji Miyamoto, Kenji Yoshida, Hisashi Kaneko
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Publication number: 20030214010Abstract: A method of manufacturing a semiconductor device, which comprises the steps of forming an intermediate layer on an insulating layer, forming a groove in the intermediate layer and the insulating layer, forming a first barrier layer on the intermediate layer, depositing a wiring layer on the first barrier layer to thereby fill the groove with the wiring layer, performing a flattening treatment of the wiring layer, removing a surface portion of the wiring to thereby permit the surface of the wiring to be recessed lower than a surface of the insulating layer, thus forming a recessed portion, forming a second barrier layer on the intermediate layer and on an inner wall of the recessed portion, performing a flattening treatment of the second barrier layer, thereby, and selectively removing the intermediate layer, exposing the insulating layer.Type: ApplicationFiled: April 29, 2003Publication date: November 20, 2003Applicant: Kabushiki Kaisha ToshibaInventors: Hiroshi Toyoda, Tetsuo Matsuda, Hisashi Kaneko, Hideaki Hirabayashi
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Patent number: 6638411Abstract: The present invention relates to a method and apparatus for separating out metal copper according to an electroplating of copper using, for example, a solution of copper sulfate to produce copper interconnections on a surface of a substrate. The substrate is brought into contact, at least once, with a processing solution containing at least one of organic substance and sulfur compound which are contained in a plating solution. Thereafter, the substrate is brought into contact with the plating solution to plate the substrate.Type: GrantFiled: January 27, 2000Date of Patent: October 28, 2003Assignees: Ebara Corporation, Kabushiki Kaisha ToshibaInventors: Koji Mishima, Mizuki Nagai, Ryoichi Kimizuka, Tetsuo Matsuda, Hisashi Kaneko
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Patent number: 6632476Abstract: After a thin liquid agent film is formed by supplying a liquid agent onto a plate-like developer holder, this liquid agent film and the surface of a substrate are opposed. The liquid agent film and the substrate are brought into contact with each other at a point by declining the substrate and moving it close to the liquid agent film, or by curving the substrate toward the liquid agent film. Then, the substrate is made parallel to the liquid agent film, and the liquid agent is supplied such that the contact area of the liquid agent film spreads over the entire surface by the interfacial tension between the liquid agent film and the substrate. Since a thin liquid agent film can be uniformly formed below the substrate, processing can be performed with a small consumption amount. Additionally, the liquid agent can be supplied to the substrate without holding air.Type: GrantFiled: March 14, 2001Date of Patent: October 14, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Hiroko Nakamura, Hisashi Kaneko, Tetsuo Matsuda
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Patent number: 6633450Abstract: A method and an apparatus for controlling a disk drive are contrived to reduce consumed electric power of a spindle motor of the disk drive while an operation continues. The disk drive has a disk storage medium, the spindle motor for rotating the disk storage medium, and a head for reading data on the disk storage medium. This control method comprises a first step of detecting a load of the spindle motor or a load capacity of a power source of the disk drive, and a second step of selecting any one of a first mode of revolving the spindle motor at a comparatively high speed and reading the data on the disk storage medium by the head, and a second mode of revolving the spindle motor at a comparatively low speed and reading the data on the disk storage medium by the head in accordance with a detected result of the first step.Type: GrantFiled: August 10, 1999Date of Patent: October 14, 2003Assignee: Fujitsu LimitedInventor: Hisashi Kaneko
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Patent number: 6632335Abstract: A plating method and apparatus for a substrate fills a metal, e.g., copper, into a fine interconnection pattern formed in a semiconductor substrate. The apparatus has a substrate holding portion 36 horizontally holding and rotating a substrate with its surface to be plated facing upward. A seal material 90 contacts a peripheral edge portion of the surface, sealing the portion in a watertight manner. A cathode electrode 88 passes an electric current upon contact with the substrate. A cathode portion 38 rotates integrally with the substrate holding portion 36. An electrode arm portion 30 is above the cathode portion 38 and movable horizontally and vertically and has an anode 98 face-down. Plating liquid is poured into a space between the surface to be plated and the anode 98 brought close to the surface to be plated. Thus, plating treatment and treatments incidental thereto can be performed by a single unit.Type: GrantFiled: December 22, 2000Date of Patent: October 14, 2003Assignees: Ebara Corporation, Kabushiki Kaisha ToshibaInventors: Junji Kunisawa, Mitsuko Odagaki, Natsuki Makino, Koji Mishima, Kenji Nakamura, Hiroaki Inoue, Norio Kimura, Tetsuo Matsuda, Hisashi Kaneko, Nobuo Hayasaka, Katsuya Okumura, Manabu Tsujimura, Toshiyuki Morita
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Patent number: 6611060Abstract: A method of forming a cap film comprises a first polishing step of performing a polishing operation at selectivity of R1 (=removal rate for the cap film/removal rate for the insulating film), and a second polishing step of performing a polishing operation at selectivity of R2 (=removal rate for the cap film/removal rate for the insulating film). Each of the polishing operations is performed by using a slurry having the condition of R1>R2. By performing the polishing operations at different selectivity, the cap film free from problems such as dishing of the cap film and the residual cap film on side walls of a recess is formed. Consequently, a semiconductor device having an excellent RC characteristic can be provided.Type: GrantFiled: October 3, 2000Date of Patent: August 26, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Toyoda, Hiroyuki Yano, Gaku Minamihaba, Dai Fukushima, Tetsuo Matsuda, Hisashi Kaneko
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Patent number: 6579785Abstract: A method of manufacturing a semiconductor device, which comprises the steps of forming an intermediate layer on an insulating layer, forming a groove in the intermediate layer and the insulating layer, forming a first barrier layer on the intermediate layer, depositing a wiring layer on the first barrier layer to thereby fill the groove with the wiring layer, performing a flattening treatment of the wiring layer, removing a surface portion of the wiring to thereby permit the surface of the wiring to be recessed lower than a surface of the insulating layer, thus forming a recessed portion, forming a second barrier layer on the intermediate layer and on an inner wall of the recessed portion, performing a flattening treatment of the second barrier layer, thereby, and selectively removing the intermediate layer, exposing the insulating layer.Type: GrantFiled: January 24, 2001Date of Patent: June 17, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Toyoda, Tetsuo Matsuda, Hisashi Kaneko, Hideaki Hirabayashi