Patents by Inventor Ho-Jin Lee

Ho-Jin Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10106417
    Abstract: Provided is a method of manufacturing graphene by unzipping doped carbon materials by an external stimulus and a graphene manufactured therefrom.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: October 23, 2018
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Sang Ouk Kim, Joonwon Lim, Ho Jin Lee
  • Patent number: 10109665
    Abstract: A semiconductor device includes a semiconductor substrate with first and second surfaces facing each other, an etch stop pattern in a trench formed in the first surface of the semiconductor substrate, a first insulating layer on the first surface of the semiconductor substrate, and a through via penetrating the semiconductor substrate and the first insulating layer. The etch stop pattern surrounds a portion of a lateral surface of the through via.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: October 23, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Jin Lee, Kwangjin Moon, Seokho Kim, Sukchul Bang, Jin Ho An, Naein Lee
  • Patent number: 10082627
    Abstract: An apparatus providing a terahertz (THz) wave may comprise at least one THz wave generator each of which generates a THz wave; at least one first phase adjuster adjusting a phase of the generated THz wave; at least one waveguide part receiving and combining the at least one phase-adjusted THz wave radiated from the at least one first phase adjuster, and guiding the combined THz wave; at least one second phase adjuster adjusting a phase of the combined THz wave from the at least one waveguide part, which is connected to the at least one waveguide part or disposed in a portion of the at least one waveguide part; and an output module outputting the THz wave guided from the at least one waveguide part.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: September 25, 2018
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Kyung Hyun Park, Il Min Lee, Eui Su Lee, Ho Jin Lee, Sang Pil Han, Hyun Soo Kim, Ki Won Moon, Dong Woo Park
  • Patent number: 10064008
    Abstract: Provided is a method and/or apparatus for providing a wireless location service using a beacon signal. A wireless location service method may include collecting a plurality of beacon signals from each of a plurality of beacon transceivers positioned around a user, and determining a current location of the user based on at least one of a virtual point and the plurality of beacon signals, the virtual point positioned in a space in which the beacon transceivers are provided.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: August 28, 2018
    Assignee: NAVER Business Platform Corp.
    Inventors: Weongi Park, Ho Jin Lee, Hyang Sub Lim, Daewoong Kim
  • Patent number: 10049997
    Abstract: A pad is disposed on a substrate. A bump structure is disposed on the pad and electrically connected to the pad. The bump structure includes a first copper layer and a second copper layer sequentially stacked on the pad and a solder ball on the second copper layer. A first X-ray diffraction (XRD) peak intensity ratio of (111) plane to (200) plane of the first copper layer is greater than a second XRD peak intensity ratio of (111) plane to (200) plane of the second copper layer.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: August 14, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ju-Il Choi, Hyoju Kim, Kwangjin Moon, Sujeong Park, Jubin Seo, Naein Lee, Ho-Jin Lee
  • Publication number: 20180226390
    Abstract: A method of manufacturing a substrate structure includes providing a first substrate including a first device region on a first surface, providing a second substrate including a second device region on a second surface, such that a width of the first device region is greater than a width of the second device region, and bonding the first substrate and the second substrate, such that the first and second device regions are facing each other and are electrically connected to each other.
    Type: Application
    Filed: January 12, 2018
    Publication date: August 9, 2018
    Inventors: Pil Kyu KANG, Seok Ho KIM, Tae Yeong KIM, Kwang Jin MOON, Ho Jin LEE
  • Publication number: 20180213363
    Abstract: A method and a system for providing integrated indoor and outdoor positioning are disclosed. The method for providing integrated positioning may comprise the steps of: receiving, by a user terminal, GPS coordinate information of the user terminal moving in an outdoor area around a building and an outdoor area within the building; and determining, by the user terminal, information on an area in which the user terminal is located and a floor on which the user terminal is located in the building, on the basis of GPS coordinate information mapped to each of the outdoor area around the building and the outdoor area within the building and the received GPS coordinate information.
    Type: Application
    Filed: March 23, 2018
    Publication date: July 26, 2018
    Inventors: Daewoong Kim, Jungmin Kang, Tae Gyu Kang, Sechun Oh, Ho Jin Lee
  • Patent number: 10019821
    Abstract: An indoor map constructing apparatus may include an information extractor configured to extract cloud point information from scan information about each point inside a target facility of which an indoor map is to be constructed, and an indoor map constructer configured to construct the indoor map of the target facility based on the cloud point information about each point.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: July 10, 2018
    Assignee: NAVER Business Platform Corp.
    Inventors: Weongi Park, Jaewook Yoo, Ho Jin Lee, Eun Yong Cheong, Byeong-Ryeol Sim, Byung-Jo Kim
  • Publication number: 20180136397
    Abstract: An apparatus providing a terahertz (THz) wave may comprise at least one THz wave generator each of which generates a THz wave; at least one first phase adjuster adjusting a phase of the generated THz wave; at least one waveguide part receiving and combining the at least one phase-adjusted THz wave radiated from the at least one first phase adjuster, and guiding the combined THz wave; at least one second phase adjuster adjusting a phase of the combined THz wave from the at least one waveguide part, which is connected to the at least one waveguide part or disposed in a portion of the at least one waveguide part; and an output module outputting the THz wave guided from the at least one waveguide part.
    Type: Application
    Filed: November 9, 2017
    Publication date: May 17, 2018
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Kyung Hyun PARK, Il Min LEE, Eui Su LEE, Ho Jin LEE, Sang Pil HAN, Hyun Soo KIM, Ki Won MOON, Dong Woo PARK
  • Publication number: 20180138137
    Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.
    Type: Application
    Filed: October 24, 2017
    Publication date: May 17, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jeong-gi JIN, Nae-in Lee, Jum-yong Park, Jin-ho Chun, Seong-min Son, Ho-jin Lee
  • Publication number: 20180138164
    Abstract: There is provided a method for fabricating a substrate structure capable of enhancing process reproducibility and process stability by trimming a bevel region of a substrate using a wafer level process. The method includes providing a first substrate including first and second surfaces opposite each other and a first device region formed at the first surface, providing a second substrate including third and fourth surfaces opposite each other and a second device region at the third surface, bonding the first substrate and the second substrate to electrically connect the first device region and the second device region, and forming a trimmed substrate. The forming the trimmed substrate includes etching an edge region of the second substrate bonded to the first substrate.
    Type: Application
    Filed: September 15, 2017
    Publication date: May 17, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ho Jin LEE, Seok Ho Kim, Kwang Jin Moon, Byung Lyul Park, Nae In Lee
  • Publication number: 20180124569
    Abstract: Disclosed are methods and systems for providing a location-based service. A location-based service providing method for determining a current location of a user terminal by interworking with a server including receiving a request to provide a location-based service, in response to the request, requesting and receiving first information about a wireless access point associated with a first building where the user terminal is located from the server; collecting second information about the wireless access point located near the user terminal, and determining a current location of the user terminal based on the first information and the second information may be provided.
    Type: Application
    Filed: December 28, 2017
    Publication date: May 3, 2018
    Applicant: NAVER Business Platform Corp.
    Inventors: Hee Su Shin, Jaewook Yoo, Ho Jin Lee, Jungmin Kang, Tae Gyu Kang, Se Chun Oh, Daewoong Kim
  • Publication number: 20180119302
    Abstract: An electroplating apparatus includes an electroplating bath including an anode installed therein and a plating solution received therein, a substrate holder configured to hold a substrate to be submerged into the plating solution and including a support surrounding the substrate and a cathode on the support to be electrically connected to a periphery of the substrate, a magnetic field generating assembly provided in the support and including at least one electromagnetic coil extending along a circumference of the substrate, and a power supply configured to current to the electromagnetic coil.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 3, 2018
    Inventors: Dong-Chan LIM, Kwang-Jin MOON, Byung-Lyul PARK, Nae-In LEE, Ho-Jin LEE
  • Publication number: 20180122721
    Abstract: A plug structure of a semiconductor chip includes a substrate, an insulating interlayer disposed on the substrate, wherein the insulating interlayer includes a pad structure disposed therein, a via hole penetrating the substrate and the insulating interlayer, wherein the via hole exposes the pad structure, an insulating pattern formed on an interior surface of the via hole, wherein the insulating pattern includes a burying portion, and the burying portion fills a notch disposed in the substrate at the interior surface of the via hole, and a plug formed on the insulating pattern within the via hole, wherein the plug is electrically connected with the pad structure.
    Type: Application
    Filed: July 27, 2017
    Publication date: May 3, 2018
    Inventors: SON-KWAN HWANG, Ho-Jin LEE, Kwang-Jin MOON, Byung-Lyul PARK, Jin-Ho AN, Nae-In LEE
  • Publication number: 20180108540
    Abstract: A method of manufacturing a semiconductor package including forming a photoresist pattern on a first surface of an interposer substrate. The interposer substrate includes an electrode zone and a scribe line zone. The interposer substrate is etched using the photoresist pattern as a mask to form a first opening and a second opening respectively on the electrode zone and the scribe line zone. An insulation layer and a conductive layer are formed on the first surface of the interposer substrate. A width of the second opening is smaller than a width of the first opening. The insulation layer contacts each of the first surface of the interposer substrate, an inner surface of the first opening, and an inner surface of the second opening.
    Type: Application
    Filed: June 29, 2017
    Publication date: April 19, 2018
    Inventors: Jae-Hyun Phee, Ho-Jin Lee, Taeseong Kim, Kwangjin Moon, Jin Ho An, Naein Lee
  • Patent number: 9941196
    Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: April 10, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ho-Jin Lee, Tae-Je Cho, Dong-Hyeon Jang, Ho-Geon Song, Se-Young Jeong, Un-Byoung Kang, Min-Seung Yoon
  • Patent number: 9941243
    Abstract: A wafer-to-wafer bonding structure includes a first wafer including a first conductive pad in a first insulating layer and a first barrier layer surrounding a lower surface and side surfaces of the first conductive pad, a second wafer including a second conductive pad in a second insulating layer and a second barrier layer surrounding a lower surface and side surfaces of the second conductive pad, the second insulating layer being bonded to the first insulating layer, and at least a portion of an upper surface of the second conductive pad being partially or entirely bonded to at least a portion of an upper surface of the first conductive pad, and a third barrier layer between portions of the first and second wafers where the first and second conductive pads are not bonded to each other.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: April 10, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-yeong Kim, Pil-kyu Kang, Seok-ho Kim, Kwang-jin Moon, Ho-jin Lee
  • Patent number: 9935037
    Abstract: A multi-stacked device includes a lower device having a lower substrate, a first insulating layer on the lower substrate, and a through-silicon-via (TSV) pad on the first insulating layer, an intermediate device having an intermediate substrate, a second insulating layer on the intermediate substrate, and a first TSV bump on the second insulating layer, an upper device having an upper substrate, a third insulating layer on the upper substrate, a second TSV bump on the third insulating layer, and a TSV structure passing through the upper substrate, the third insulating layer, the second insulating layer, and the intermediate substrate to be connected to the first TSV bump, the second TSV bump, and the TSV pad. An insulating first TSV spacer between the intermediate substrate and the TSV structure and an insulating second TSV spacer between the upper substrate and the TSV structure are spaced apart along a stacking direction.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: April 3, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Pil-kyu Kang, Ho-jin Lee, Byung-lyul Park, Tae-yeong Kim, Seok-ho Kim
  • Publication number: 20180069956
    Abstract: A watch phone and a method for handling an incoming call using the watch phone are provided. In the watch phone, a display device includes a touch screen panel and a display, turns off the touch screen panel in a watch mode, turns on the touch screen panel in an idle mode or upon receipt of an incoming call, and displays at least two areas for call connection and call rejection, upon receipt of the incoming call. A single mode selection key selects one of the watch mode and the idle mode. A controller performs control operations so that the touch screen panel is turned off in the watch mode and is turned on in the idle mode or upon receipt of the incoming call, and connects or rejects the incoming call, when the at least two areas for call connection or call rejection, which are displayed upon receipt of the incoming call, are pointed to or dragged to.
    Type: Application
    Filed: November 13, 2017
    Publication date: March 8, 2018
    Inventors: Shi-Yun CHO, Ji-Hyun JUNG, Ho-Jin LEE, Young-Min LEE, Ho-Seong SEO, Youn-Ho CHOI
  • Publication number: 20180053797
    Abstract: A semiconductor device includes a semiconductor substrate with first and second surfaces facing each other, an etch stop pattern in a trench formed in the first surface of the semiconductor substrate, a first insulating layer on the first surface of the semiconductor substrate, and a through via penetrating the semiconductor substrate and the first insulating layer. The etch stop pattern surrounds a portion of a lateral surface of the through via.
    Type: Application
    Filed: June 22, 2017
    Publication date: February 22, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ho-Jin LEE, Kwangjin MOON, Seokho KIM, Sukchul BANG, Jin Ho AN, Naein LEE