Patents by Inventor Hoon Ahn

Hoon Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210313552
    Abstract: Disclosed is a coating apparatus for producing an electrode, which has a reduced defect rate in the coating process. The coating apparatus includes a die unit having an inlet through which the electrode slurry is introduced and an inner space for accommodating the introduced electrode slurry; a shim unit mounted in the die unit and configured to form an outlet together with the die unit so that the electrode slurry is discharged therethrough; and a cover member configured to surround an outer surface of the die unit and the shim unit so that the electrode slurry is not leaked at the outer surface, except for the outlet.
    Type: Application
    Filed: June 16, 2021
    Publication date: October 7, 2021
    Applicant: LG Chem, Ltd.
    Inventors: Woo-Ha Kim, In-Seong Kim, Il-Jae Moon, Byoung-Hoon Ahn, Jung-Min Yang, Sang-Hoon Choy
  • Publication number: 20210300984
    Abstract: The present invention relates to long-acting insulin analogues having an increased in vivo half-life in which the amino acid at position 22 of the B-chain of native insulin is substituted and one or more amino acids of the A-chain or B-chain of native insulin are additionally substituted, and to long-acting insulin analogue derivatives having a further increased in vivo half-life in which an albumin-binding domain is additionally fused to the long-acting insulin analogues. The insulin analogues or insulin analogue derivatives according to the present invention have a significantly increased in vivo half-life, and thus can provide convenience to diabetic patients who self-administer insulin by injection.
    Type: Application
    Filed: July 19, 2019
    Publication date: September 30, 2021
    Inventors: Kyong Hoon AHN, Oh-Byung KWON, Seung Woo KIM
  • Patent number: 11133266
    Abstract: A method of fabricating a semiconductor device comprises forming first and second align keys in a wafer, the second align key apart from the first align key, forming third and fourth align keys in the wafer, the third align key apart from the second align key, the fourth align key apart from the third align key, forming a fifth align key in the wafer, the fifth align key apart from the fourth align key, forming a first line pattern in the wafer using the second and third align keys, forming a second line pattern in the wafer using the fourth and fifth align keys, forming a first interposer including the first line pattern by cutting a space between the first and second align keys, and forming a second interposer, the second interposer including the second line pattern by cutting a space between the third and fourth align keys.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: September 28, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shaofeng Ding, Jeong Hoon Ahn, Yun Ki Choi
  • Publication number: 20210296229
    Abstract: A semiconductor device includes a substrate, a first electrode including a first hole, a first dielectric layer on an upper surface of the first electrode and on an inner surface of the first hole, a second electrode on the first dielectric layer, a second dielectric layer on the second electrode, a third electrode on the second dielectric layer and including a second hole, and a first contact plug extending through the second electrode and the second dielectric layer and extending through the first hole and the second hole. A sidewall of the first contact plug is isolated from direct contact with the sidewall of the first hole and a sidewall of the second hole, and has a step portion located adjacent to an upper surface of the second electrode.
    Type: Application
    Filed: June 7, 2021
    Publication date: September 23, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jinho PARK, Shaofeng DING, Yongseung BANG, Jeong Hoon AHN
  • Patent number: 11127936
    Abstract: Disclosed is a coating apparatus for producing an electrode, which has a reduced defect rate in the coating process. The coating apparatus includes a die unit having an inlet through which the electrode slurry is introduced and an inner space for accommodating the introduced electrode slurry; a shim unit mounted in the die unit and configured to form an outlet together with the die unit so that the electrode slurry is discharged therethrough; and a cover member configured to surround an outer surface of the die unit and the shim unit so that the electrode slurry is not leaked at the outer surface, except for the outlet.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: September 21, 2021
    Inventors: Woo-Ha Kim, In-Seong Kim, Il-Jae Moon, Byoung-Hoon Ahn, Jung-Min Yang, Sang-Hoon Choy
  • Patent number: 11121361
    Abstract: The present invention provides a method of preparing a slurry for a secondary battery positive electrode which includes forming a first mixture in a paste state by adding a lithium iron phosphate-based positive electrode active material, a conductive agent, a binder, and a solvent, and preparing a slurry for a positive electrode by mixing while further adding a solvent to the first mixture in the paste state.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: September 14, 2021
    Inventors: Byoung Hoon Ahn, Sang Hoon Choy, Chang Wan Koo, Hyun Chul Ha
  • Patent number: 11114524
    Abstract: A semiconductor device including a first electrode on a substrate, a second electrode on the first electrode, a first dielectric layer between the first electrode and the second electrode; a third electrode on the second electrode, a second dielectric layer between the second electrode and the third electrode, and a first contact plug penetrating the third electrode and contacting the first electrode, the first contact plug contacts a top surface of the third electrode and a side surface of the third electrode.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: September 7, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shaofeng Ding, Jinho Park, Yongseung Bang, Jeong Hoon Ahn
  • Publication number: 20210249694
    Abstract: Provided is a method for manufacturing an all-solid-state battery which allows a solid electrolyte layer and an electrode to be in sufficiently close in contact with each other without deformation of the electrode shape or damages upon the electrode. The method for manufacturing an all-solid-state battery includes applying slurry for a solid electrolyte layer to the surface of an electrode active material layer to form a patterned solid electrolyte layer, and carrying out pressurization to form a solid electrolyte layer.
    Type: Application
    Filed: November 1, 2019
    Publication date: August 12, 2021
    Applicant: LG CHEM, LTD.
    Inventors: Byoung-Hoon AHN, Sang-Kyun LEE, Hae-Kang CHUNG, Baeck-Boem CHOI, Sang-Hoon CHOY
  • Publication number: 20210242147
    Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The semiconductor device includes a first dielectric layer including a first pad, a second dielectric layer on the first dielectric layer, a through electrode that penetrates the second dielectric layer and is electrically connected to the first pad, an upper passivation layer on the second dielectric layer, a second pad on the upper passivation layer, and an upper barrier layer between the upper passivation layer and the second pad. The first pad and the through electrode include a first material. The second pad includes a second material that is different from the first material of the first pad and the through electrode. The second pad includes a first part on the upper passivation layer, and a second part that extends from the first part into the upper passivation layer and is connected to the through electrode.
    Type: Application
    Filed: September 2, 2020
    Publication date: August 5, 2021
    Inventors: JINHO PARK, CHIN KIM, YONGSEUNG BANG, JIYEON BAEK, JEONG HOON AHN
  • Publication number: 20210242203
    Abstract: A semiconductor device includes a substrate including a logic cell region and a connection region, a dummy transistor on the connection region, an intermediate connection layer on the dummy transistor, a first metal layer on the intermediate connection layer, an etch stop layer between the intermediate connection layer and the first metal layer, a through contact below the first metal layer penetrating the connection region, an upper portion of the through contact protruding above the etch stop layer, and a protection insulating pattern on the etch stop layer covering the upper portion of the through contact. The protection insulating pattern covers an upper side surface of the through contact and a top surface of the through contact.
    Type: Application
    Filed: September 28, 2020
    Publication date: August 5, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Shaofeng DING, Minguk KANG, Jihyung KIM, Jeong Hoon AHN, Haeri YOO, Yun Ki CHOI
  • Publication number: 20210233842
    Abstract: A semiconductor device includes a substrate having a first region, a second region, a first buffer region, and a second buffer region. A plurality of conductive lines is disposed on the first region of the substrate. An inductor is disposed on the second region of the substrate, and a dummy pattern is disposed on the first buffer region of the substrate. The first buffer region is provided between the first region and the second region. The second buffer region is provided between the first buffer region and the second region.
    Type: Application
    Filed: April 15, 2021
    Publication date: July 29, 2021
    Inventors: JOON-NYUNG LEE, JEONG HOON AHN
  • Publication number: 20210233862
    Abstract: A semiconductor may include a first inter metal dielectric (IMD) layer, a first blocking layer on the first IMD layer, a metal wiring and a second blocking layer. The first inter metal dielectric (IMD) layer may be formed on a substrate, the first IMD layer may include a low-k material having a dielectric constant lower than a dielectric constant of silicon oxide. The first blocking layer may be formed on the first IMD layer. The first blocking layer may include an oxide having a dielectric constant higher than the dielectric constant of the first IMD layer. The metal wiring may be through the first IMD layer and the first blocking layer. The second blocking layer may be formed on the metal wiring and the first blocking layer. The second blocking layer may include a nitride. The first and second blocking layers may reduce or prevent from the out gassing, so that a semiconductor device may have good characteristics.
    Type: Application
    Filed: April 13, 2021
    Publication date: July 29, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jun-Kwan KIM, Jae-Wha PARK, Sang-Hoon AHN
  • Publication number: 20210233860
    Abstract: An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.
    Type: Application
    Filed: April 14, 2021
    Publication date: July 29, 2021
    Inventors: SU-HYUN BARK, SANG-HOON AHN, YOUNG-BAE KIM, HYEOK-SANG OH, WOO-JIN LEE, HOON-SEOK SEO, SUNG-JIN KANG
  • Patent number: 11049810
    Abstract: An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: June 29, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Su-Hyun Bark, Sang-Hoon Ahn, Young-Bae Kim, Hyeok-Sang Oh, Woo-Jin Lee, Hoon-Seok Seo, Sung-Jin Kang
  • Patent number: 11043456
    Abstract: A semiconductor device includes a substrate, a first electrode including a first hole, a first dielectric layer on an upper surface of the first electrode and on an inner surface of the first hole, a second electrode on the first dielectric layer, a second dielectric layer on the second electrode, a third electrode on the second dielectric layer and including a second hole, and a first contact plug extending through the second electrode and the second dielectric layer and extending through the first hole and the second hole. A sidewall of the first contact plug is isolated from direct contact with the sidewall of the first hole and a sidewall of the second hole, and has a step portion located adjacent to an upper surface of the second electrode.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: June 22, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinho Park, Shaofeng Ding, Yongseung Bang, Jeong Hoon Ahn
  • Publication number: 20210184218
    Abstract: Complex particles for a negative electrode active material according to the present disclosure have no problem with reduced capacity and output by virtue of sufficient electrochemical reaction sites between a solid electrolyte and an electrode active material. The complex particles according to the present disclosure include carbon particles of a carbon material such as flaky graphite, which are spherical in shape by shape modification, and a solid electrolyte and a conductive material filled between the particles, and thus have the increased contact area between the active material and the solid electrolyte increases, and ion conduction and electron conduction paths extended and maintained to the inside of the active material particles.
    Type: Application
    Filed: May 24, 2019
    Publication date: June 17, 2021
    Applicant: LG Chem, Ltd.
    Inventors: Byoung-Hoon Ahn, Kyung-Taek Kim, Ki-Tae Kim, Chan-Soo Jun, Sang-Hoon Choy
  • Patent number: D930588
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: September 14, 2021
    Assignee: ITM SEMICONDUCTOR CO., LTD.
    Inventors: Hyuk Hwi Na, Ho Seok Hwang, Young Seok Kim, Sang Hoon Ahn, Jae Ku Park, Sung Hee Wang, Eun Bin Lee
  • Patent number: D932436
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: October 5, 2021
    Assignee: ITM SEMICONDUCTOR CO., LTD.
    Inventors: Hyuk Hwi Na, Ho Seok Hwang, Young Seok Kim, Sang Hoon Ahn, Jae Ku Park, Sung Hee Wang, Eun Bin Lee
  • Patent number: D932437
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: October 5, 2021
    Assignee: ITM SEMICONDUCTOR CO., LTD.
    Inventors: Hyuk Hwi Na, Ho Seok Hwang, Young Seok Kim, Sang Hoon Ahn, Jae Ku Park, Sung Hee Wang, Eun Bin Lee
  • Patent number: D932438
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: October 5, 2021
    Assignee: ITM SEMICONDUCTOR CO., LTD.
    Inventors: Hyuk Hwi Na, Ho Seok Hwang, Young Seok Kim, Sang Hoon Ahn, Jae Ku Park, Sung Hee Wang, Eun Bin Lee