Abstract: An electronic device is provided.

Abstract: Etchant compositions described herein include etchant compositions for etching a silicon film and may include nitric acid, fluoric acid, phosphoric acid, acetic acid, a nitrogen compound, and water. The nitrogen compound may include fluorine (F), phosphorus (P), and/or carbon (C). Also described are methods of manufacturing an integrated circuit (IC) device. The methods may include providing a structure in which a silicon film doped at a first dopant concentration and an epitaxial film doped at a second dopant concentration are stacked. The second dopant concentration may be different from the first dopant concentration. The silicon film may be selectively etched from the structure by using an etchant composition.

Abstract: An apparatus and method for controlling temperature of automatic transmission fluid, and a vehicle system are provided. The apparatus includes a determination device that determines whether a temperature difference between the temperature of the automatic transmission fluid and a target temperature thereof satisfies a heating control condition of the automatic transmission fluid at the start of charging. A then adjusts the temperature of the automatic transmission fluid by outputting an operation control signal for at least one driving unit of a thermal management system, when the temperature difference satisfies the heating control condition of the automatic transmission fluid.

Abstract: Disclosed are a refractive optical screen and a floating hologram system using the same. The refractive optical screen is a refractive optical screen which refracts incident light beams and adjusts a travelling direction of the light beams, and includes a prism array in which a plurality of prisms refracting one or more light beams toward a viewing direction of a viewer located at the front side of the refractive optical screen is arranged in a line, and one or more virtual images generated by the one or more refracted light beams simultaneously form a floating hologram arranged in the viewing direction.

Abstract: Embodiments of the inventive concepts provide a method of manufacturing a semiconductor device and a cleaning composition for an adhesive layer. The method includes preparing a semiconductor substrate to which an adhesive layer adheres, removing the adhesive layer from the semiconductor substrate, and applying a cleaning composition to the semiconductor substrate to remove a residue of the adhesive layer. The cleaning composition includes a solvent including a ketone compound and having a content that is equal to or greater than 40 wt % and less thaadminn 90 wt %, quaternary ammonium salt, and primary amine.

Abstract: A light-emitting device includes a light-emitting layer between a first electrode and a second electrode, he light emitted from the light-emitting device may display a white color, the light-emitting layer may include a plurality of emission stacks, each of the emission stacks includes at least one emission material layer, one of the emission stacks may include a stacked structure of a red emission material layer and a blue emission material layer, thus improving the white balance and increasing color viewing angle.

Abstract: A metal plate to be used in the manufacture of a deposition mask comprises: a base metal plate; and a surface layer disposed on the base metal plate, wherein the surface layer includes elements different from those of the base metal plate, or has a composition ratio different from that of the base metal plate, and an etching rate of the base metal plate is greater than the etching rate of the surface layer. An embodiment includes a manufacturing method for a deposition mask having an etching factor greater than or equal to 2.5. The deposition mask of the embodiment includes a deposition pattern region and a non-deposition region, the deposition pattern region includes a plurality of through-holes, the deposition pattern region is divided into an effective region, a peripheral region, and a non-effective region, and through-holes can be formed in the effective region and the peripheral region.

Abstract: A semiconductor memory device comprises a substrate, first and second lower electrode groups on the substrate and including a plurality of first and second lower electrodes, respectively, and first and second support patterns on side walls of and connecting each of the first and second lower electrodes, respectively. The first lower electrodes include a first center lower electrode arranged within a hexagonal shape defined by first edge lower electrodes. The second lower electrodes include a second center lower electrode arranged within a hexagonal shape defined by second edge lower electrodes. The first center lower electrode is spaced apart from each of the first edge lower electrodes in different first to third directions. The first support pattern is immediately adjacent to the second support pattern. The first center lower electrode is spaced apart from the second center lower electrode in a fourth direction different from the first to third directions.

Abstract: A semiconductor device includes a gate stack including a gate insulating layer and a gate electrode on the gate insulating layer. The gate insulating layer includes a first dielectric layer and a second dielectric layer on the first dielectric layer, and a dielectric constant of the second dielectric layer is greater than a dielectric constant of the first dielectric layer. The semiconductor device also includes a first spacer on a side surface of the gate stack, and a second spacer on the first spacer, wherein the second spacer includes a protruding portion extending from a level lower than a lower surface of the first spacer towards the first dielectric layer, and a dielectric constant of the second spacer is greater than the dielectric constant of the first dielectric layer and less than a dielectric constant of the first spacer.

Abstract: A semiconductor memory device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region, the boundary element isolation layer being in a boundary element isolation recess and including first and second boundary liner layers extending along a profile of the boundary element isolation recess and a first gate structure on the core region and at least a part of the boundary element isolation layer, wherein the first gate structure includes a first high dielectric layer, and a first gate insulating pattern below the first high dielectric layer, with a top surface of the substrate being a base reference level, the first gate insulating pattern does not overlap a top surface of the first boundary liner layer, and wherein the first gate insulating pattern includes a first_1 gate insulating pattern between a top surface of the second boundary liner layer and a bottom surface of the first high

Abstract: A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide a method for manufacturing a semiconductor device, and a semiconductor device produced thereby, that comprises an interposer without through silicon vias.

Abstract: There is disclosed an augmented reality (AR) glasses device including: a camera, a transparent display, a communication circuit, a memory storing images of a plurality of external electronic devices, and a processor. The processor may be configured to control the AR glasses device to: acquire an image including an image of at least one external electronic device, acquire running application information of the at least one external electronic device, identify a first external electronic device corresponding to a gaze from among the at least one external electronic device from the acquired image, determine whether a specified application is running in the first external electronic device based on the running application information, and connect to the first external electronic device using a communication circuit, based on the specified application running.

Abstract: A hydro engine mount for a vehicle may include a locking body including a plurality of locking portions; a body plate including a plurality of fastening grooves configured to be fastened to the plurality of locking portions, wherein a main rubber is mounted in the body plate; and a diaphragm stacked between the main rubber and the locking body.

Abstract: Provided is an analysis method for a crack rate of an electrode active material of an electrode, comprising the steps of: forming an electrode including an electrode active material, a binder, and a conductive material; impregnating the electrode with a resin and visualizing material regions including the electrode active material, the binder, and the conductive material which are included in the electrode, and a pore region; cutting the electrode and forming an electrode cross-section sample; photographing a cross section of the electrode cross-section sample using a scanning electron microscope and obtaining a cross-sectional image; performing primary image processing on the cross-sectional image and extracting total surface area pixels of the electrode active material; performing secondary image processing on the cross-sectional image and extracting total boundary pixels of the electrode active material; and calculating a crack rate of the electrode active material of the electrode in the cross-sectional i

Abstract: A metal plate to be used in the manufacture of a deposition mask comprises: a base metal plate; and a surface layer disposed on the base metal plate, wherein the surface layer includes elements different from those of the base metal plate, or has a composition ratio different from that of the base metal plate, and an etching rate of the base metal plate is greater than the etching rate of the surface layer. An embodiment includes a manufacturing method for a deposition mask having an etching factor greater than or equal to 2.5. The deposition mask of the embodiment includes a deposition pattern region and a non-deposition region, the deposition pattern region includes a plurality of through-holes, the deposition pattern region is divided into an effective region, a peripheral region, and a non-effective region, and through-holes can be formed in the effective region and the peripheral region.

Abstract: The present disclosure provides a system and method for determining whether to start an engine. The system includes an engine configured to provide driving force for a vehicle through combustion of fuel, a motor configured to provide driving force for the vehicle using electrical energy, an engine clutch connecting the engine and a drive shaft, and a controller configured to control engagement of the engine clutch and starting of the engine. The controller calculates a predicted vehicle speed at the time of engagement of the engine clutch based on the current vehicle speed upon a request for passive run driving of the vehicle. The controller determines whether to start the engine by comparing the predicted vehicle speed with a reference vehicle speed.

Abstract: A metal plate to be used in the manufacture of a deposition mask comprises: a base metal plate; and a surface layer disposed on the base metal plate, wherein the surface layer includes elements different from those of the base metal plate, or has a composition ratio different from that of the base metal plate, and an etching rate of the base metal plate is greater than the etching rate of the surface layer. An embodiment includes a manufacturing method for a deposition mask having an etching factor greater than or equal to 2.5. The deposition mask of the embodiment includes a deposition pattern region and a non-deposition region, the deposition pattern region includes a plurality of through-holes, the deposition pattern region is divided into an effective region, a peripheral region, and a non-effective region, and through-holes can be formed in the effective region and the peripheral region.

Abstract: A clutch control method for a hybrid vehicle with a DCT is provided. The method includes determining an energy-saving possible period based on a selection state of shifting ranges, operation states of an accelerator pedal and a brake pedal, and the gradient of a road on which the vehicle is driven. An operation current is set for maintaining a clutch, which is configured to engage the first gear, engaged as 0 A in response to determining that a current state of the vehicle is in the energy-saving possible period.

Abstract: The present disclosure provides a semiconductor memory device capable of improving reliability and performance. The semiconductor memory device comprises a substrate including a cell region and a peripheral region around the cell region, a cell region isolation film which defines the cell region, a bit line structure in the cell region, a first peripheral gate structure on the peripheral region of the substrate, the first peripheral gate structure comprising a first peripheral gate conduction film and a first peripheral capping film on the first peripheral gate conduction film, a peripheral interlayer insulating film around the first peripheral gate structure and an insertion interlayer insulating film on the peripheral interlayer insulating film and the first peripheral gate structure, and including a material different from the peripheral interlayer insulating film. An upper face of the peripheral interlayer insulating film is lower than an upper face of the first peripheral capping film.

Abstract: A semiconductor memory device includes a third insulating pattern and a first insulating pattern on a substrate, the third insulating pattern and the first insulating pattern being spaced apart from each other in a first direction that is perpendicular to the substrate such that a bottom surface of the third insulating pattern and a top surface of the first insulating pattern face each other, a gate electrode between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and including a first side extending between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and a second insulating pattern that protrudes from the first side of the gate electrode by a second width in a second direction, the second direction being different from the first direction.