Abstract: In a substrate processing method, a cleaning process is performed at a first temperature to remove a portion of a cumulative layer that is deposited within a chamber by deposition processes (step 1). The deposition processes are performed at the first temperature on a plurality of substrates within the chamber respectively (step 2). The step 1 and the step 2 are performed alternately and repeatedly.

Abstract: A device and method for recognizing an object included in an input image are provided, the device for recognizing the object included in the input image includes a memory in which at least one program is stored; a camera configured to capture an environment around the device; and at least one processor configured to execute the at least one program to recognize an object included in an input image, wherein the at least one program includes instructions to: obtain the input image by controlling the camera; obtain information about the environment around the device that obtains the input image; determine, based on the information about the environment, a standard for using a plurality of feature value sets in a combined way, the plurality of feature value sets being used to recognize the object in the input image; and recognize the object included in the input image, by using the plurality of feature value sets based on the determined standard for using the plurality of feature value sets in the combined way.

Abstract: A silicon layer etchant composition and associated methods, the composition including about 1 wt % to about 20 wt % of an alkylammonium hydroxide; about 1 wt % to about 30 wt % of an amine compound; about 0.01 wt % to about 0.2 wt % of a nonionic surfactant including both a hydrophobic group and a hydrophilic group; and water, all wt % being based on a total weight of the silicon layer etchant composition.

Abstract: A semiconductor device includes a lower stack structure that includes a lower word line, an upper stack structure that is on the lower stack structure and includes an upper word line, a decoder that is adjacent to the lower stack structure and the upper stack structure, a signal interconnection that is connected to the decoder, a lower selector that is connected to the signal interconnection and further connected to the lower word line, and an upper selector that is connected to the signal interconnection, isolated from direct contact with the lower selector, and further connected to the upper word line.

Abstract: A semiconductor device includes a semiconductor substrate and a connection terminal, including a base pillar, on the semiconductor substrate. An insulation layer is formed on the semiconductor substrate, the insulation layer including an opening in the insulation layer through which the base pillar extends, wherein a side wall of the insulation layer defining the opening includes a horizontal step at a level that is lower than an uppermost portion of the base pillar.

Abstract: A semiconductor device includes a semiconductor substrate including a chip region and an edge region around the chip region, a lower insulating layer on the semiconductor substrate, a chip pad on the lower insulating layer on the chip region, an upper insulating layer provided on the lower insulating layer to cover the chip pad, the upper and different insulating layers including different materials, and a redistribution chip pad on the chip region and connected to the chip pad. The upper insulating layer includes a first portion on the chip region having a first thickness, a second portion on the edge region having a second thickness, and a third portion on the edge region, the third portion extending from the second portion, spaced from the first portion, and having a decreasing thickness away from the second portion. The second thickness is smaller than the first thickness.

Abstract: An etchant composition and a method of fabricating a semiconductor device, the composition including an inorganic acid; about 0.01 parts by weight to about 0.5 parts by weight of colloidal silica; about 0.01 parts by weight to about 30 parts by weight of an ammonium-based additive; and about 20 parts by weight to about 50 parts by weight of a solvent, all parts by weight being based on 100 parts by weight of the inorganic acid.

Abstract: One embodiment of the present invention relates to a rotor and a motor having same, the rotor comprising: a rotor core; and a plurality of magnets arranged to be spaced apart from each other on an outer circumferential surface of the rotor core, wherein the rotor core includes: a body; and protrusions protruding obliquely inward at a predetermined angle from an inner circumferential surface of the body, wherein a predetermined gap (G1) is formed between the inner circumferential surface of the body and the end of each of the protrusions. Accordingly, the rotor and the motor having the same may minimize the amount of change in the outer circumferential surface of the rotor core by using the protrusions. As a result, it is possible to inhibit separation of the magnets attached to the outer circumferential surface of the rotor core.

Abstract: A semiconductor memory includes metallic lines on a substrate and including an uppermost metallic line, a semiconductor conduction line on the uppermost metallic line, a vertical structure penetrating the semiconductor conduction line and metallic lines, and including a vertical structure that includes an upper channel film, a first lower channel film, and an upper connection channel film connecting the upper channel film and the first lower channel film between a bottom of the semiconductor conduction line and a bottom of the uppermost metallic line, and a first cutting line through the metallic lines and the semiconductor conduction line, and including a first upper cutting line through the semiconductor conduction line, and a first lower cutting line through the plurality of metallic lines, a width of the first upper cutting line being greater than a width of an extension line of a sidewall of the first lower cutting line.

Abstract: A semiconductor device including a semiconductor substrate including a chip region and an edge region around the chip region; a lower dielectric layer and an upper dielectric layer on the semiconductor substrate; a redistribution chip pad that penetrates the upper dielectric layer on the chip region and is connected a chip pad; a process monitoring structure on the edge region; and dummy elements in the edge region and having an upper surface lower than an upper surface of the upper dielectric layer.

Abstract: A fusing apparatus for an image forming apparatus includes a fusing belt having a sidewall that faces the fusing bel, a guide member, disposed on the sidewall and having a lower portion disposed above a lower portion of the bushing, and a ring member, disposed between the guide member and the fusing belt. The ring member can be deflected toward the sidewall in a gap which is provided below the lower portion of the guide member and between the ring member and the sidewall.

Abstract: A semiconductor device including a substrate including a chip region and an edge region; integrated circuit elements on the chip region; an interlayer insulating layer covering the integrated circuit elements; an interconnection structure on the interlayer insulating layer and having a side surface on the edge region; a first and second conductive pattern on the interconnection structure, the first and second conductive patterns being electrically connected to the interconnection structure; a first passivation layer covering the first and second conductive patterns and the side surface of the interconnection structure; and a second passivation layer on the first passivation layer, wherein the second passivation layer includes an insulating material different from the first passivation layer, and, between the first and second conductive patterns, the second passivation layer has a bottom surface that is located at a vertical level lower than a top surface of the first conductive pattern.

Abstract: Semiconductor packages may include a semiconductor chip on a substrate and an under-fill layer between the semiconductor chip and the substrate. The semiconductor chip may include a semiconductor substrate including first and second regions, and an interlayer dielectric layer that may cover the semiconductor substrate and may include connection lines. First conductive pads may be on the first region and may be electrically connected to some of the connection lines. Second conductive pads may be on the second region and may be electrically isolated from all of the connection lines. The semiconductor chip may also include a passivation layer that may cover the interlayer dielectric layer and may include holes that may expose the first and second conductive pads, respectively. On the second region, the under-fill layer may include a portion that may be in one of the first holes and contact one of the second conductive pads.

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a conductive pad on a first surface of the semiconductor substrate, a passivation layer on the first surface of the semiconductor substrate, the passivation layer having a first opening that exposes the conductive pad, an organic dielectric layer on the passivation layer, the organic dielectric layer having a second opening, and a bump structure on the conductive pad and in the first and second openings. The organic dielectric layer includes a material different from a material of the passivation layer. The second opening is spatially connected to the first opening and exposes a portion of the passivation layer. The bump structure includes a pillar pattern in contact with the passivation layer and the organic dielectric layer.

Abstract: The method includes forming a first dielectric layer on a substrate, forming a via in the first dielectric layer, sequentially forming a first metal pattern, a first metal oxide pattern, a second metal pattern, and an antireflective pattern on the first dielectric layer, and performing an annealing process to react the first metal oxide pattern and the second metal pattern with each other to form a second metal oxide pattern. The forming the second metal oxide pattern includes forming the second metal oxide pattern by a reaction between a metal element of the second metal pattern and an oxygen element of the first metal oxide pattern.

Abstract: A method performed using at least one processor to facilitate word learning, the method including selecting a plurality of words to be learned; generating a learning word pool including the plurality of words to be learned; selecting a determined number of words from the learning word pool; generating a learning list including the determined number of words; displaying a first word included in the learning list; receiving a selection of whether to maintain the displayed first word in the learning list or replace the displayed first word with an alternate word; excluding the displayed first word from the learning list in response to the selection to replace the displayed first word; and adding the alternate word to the learning list in response to the excluding.

Abstract: Provided is a nonvolatile memory device. The nonvolatile memory device includes a conductive plate, a barrier conductive film extending along a surface of the conductive plate, a mold structure including a plurality of gate electrodes sequentially stacked on the barrier conductive film, a channel hole penetrating the mold structure to expose the barrier conductive film, an impurity pattern being in contact with the barrier conductive film, and formed in the channel hole, and a semiconductor pattern formed in the channel hole, extending from the impurity pattern along a side surface of the channel hole, and intersecting the plurality of gate electrodes.

Abstract: A semiconductor memory device includes; a lower stacked structure including lower metallic lines stacked in a first direction on a substrate, an upper stacked structure including a first upper metallic line and a second upper metallic line sequentially stacked on the lower stacked structure, a vertical structure penetrating the upper stacked structure and lower stacked structure and including a channel film, a connection pad disposed on the vertical structure, contacted with the channel film and doped with N-type impurities, a first cutting line cutting the lower metallic lines, the first upper metallic line and the second upper metallic line, a second cutting line spaced apart from the first cutting line in a second direction different from the first direction, and cutting the lower metallic lines, the first upper metallic line and the second upper metallic line, and sub-cutting lines cutting the first upper metallic line and the second upper metallic line between the first cutting line and the second cuttin

Abstract: A hybrid vehicle is provided and includes an input that receives user selection for terrain mode and a HSG connected to the engine to operate as a start motor to turn on the engine. The HSG operates as a generator that performs idle charging when the engine is turned on. A battery is electrically connected to the HSG. A controller configured perform idle charging when SOC of the battery is less than or equal to a first SOC through the HSG by turning on the engine.

Abstract: A system and method for controlling a hybrid electric vehicle using a driving tendency are provided. The method includes determining a driving tendency level based on data to determine a driving tendency of a driver and determining a target engine torque using an engine torque map based on a vehicle speed and a required torque. Whether the driving tendency level corresponds to a predetermined level is determined as well as whether the required torque is equal to or greater than a torque that corresponds to an optimal operating point of an engine when the driving tendency level corresponds to the predetermined level. The target engine torque is then adjusted when the required torque is equal to or greater than the torque that corresponds to the optimal operating point of the engine.