Abstract: A method includes fabricating a first transistor and a second transistor on a substrate and fabricating a first conducting line and a second conducting line in a first metal layer. The method also includes connecting a gate of the first transistor to the first conducting line and connecting a gate of the second transistor to the second conducting line. The first conducting line and the second conducting line are parallel and adjacent to each other in the first metal layer above the first transistor and the second transistor. The method still includes connecting a source and a drain of the first transistor to a third conducting line.

Abstract: The present disclosure relates to a transistor device. The transistor device includes a plurality of source contacts disposed over a substrate. A plurality of gate structures are disposed over the substrate. The plurality of gate structures wrap around one or more of the plurality of source contacts in one or more closed loops. A drain contact is disposed over the substrate. The drain contact continuously wraps around one or more of the plurality of gate structures as a continuous structure. The plurality of gate structures are separated from the drain contact by a first distance and are separated from a source contact of the plurality of source contacts by a second distance. The second distance is different than the first distance.

Abstract: Disclosed is a die-bonding method which provides a target substrate having a circuit structure with multiple electrical contacts and multiple semiconductor elements each semiconductor element having a pair of electrodes, arranges the multiple semiconductor elements on the target substrate with the pair of electrodes of each semiconductor element aligned with two corresponding electrical contacts of the target substrate, and applies at least one energy beam to join and electrically connect the at least one pair of electrodes of every at least one of the multiple semiconductor elements and the corresponding electrical contacts aligned therewith in a heating cycle by heat carried by the at least one energy beam in the heating cycle. The die-bonding method delivers scattering heated dots over the target substrate to avoid warpage of PCB and ensures high bonding strength between the semiconductor elements and the circuit structure of the target substrate.

Abstract: A thin film transistor substrate includes a substrate, a first conductive element and a semiconductor. The first conductive element is disposed on the substrate and includes a trace portion extending along a first direction and a protrusive portion extending from the trace portion. The semiconductor is disposed on the substrate. The trace portion has a first edge and a second edge opposite to the first edge, and the protrusive portion has at least one curved edge connecting with the second edge. In a top view, a virtual extending line disposes between the trace portion and the protrusive portion, the virtual extending line overlaps the second edge. At least a part of the semiconductor extends beyond the virtual extending line along a second direction vertical to the first direction.

Abstract: A method for detecting dust mite antigens includes the steps of collecting a dust sample, applying an extraction and cleanup procedure for dust mite antigens from the dust sample in order to obtain a sample solution ready for measurement, and placing the sample solution on a SERS chip without immunological modification and under a Raman spectrometer for SERS detection in order to identify whether any dust mite antigens exist in the sample solution.

Abstract: Various embodiments of the present disclosure are directed toward an integrated chip including an undoped layer overlying a substrate. A first barrier layer overlies the undoped layer. A doped layer overlies the first barrier layer. Further, a second barrier layer overlies the first barrier layer, where the second barrier layer is laterally offset from a perimeter of the doped layer by a non-zero distance. The first and second barrier layers comprise a same III-V semiconductor material. A first atomic percentage of a first element within the first barrier layer is less than a second atomic percentage of the first element within the second barrier layer.

Abstract: A method (of decoupling from voltage variations in a first voltage drop between first and second reference voltage rails) includes: electrically coupling one or more components to form a decoupling capacitance (decap) circuit; electrically coupling one or more components to form a filtered biasing circuit; and making an unswitched series electrical coupling of the decap circuit and the filtered biasing circuit between the first and second reference voltage rails.

Abstract: A charging gun is applicable to a charger station. The charging gun includes a charging gun body and a charge state display apparatus. The charge state display apparatus includes a charge state sensor, a display light module, and a controller. The charge state sensor is configured to sense a charge state of the charger station. The display light module is arranged on the charging gun body. The display light module includes a first light-emitting element, a second light-emitting element, and a third light-emitting element. The controller is electrically connected to the charge state sensor and the display light module. The controller is configured to control the first light-emitting element, the second light-emitting element, or the third light-emitting element to emit light according to the charge state.

Abstract: A fluid pipe magnetization unit includes a ferromagnetism casing, a plurality of magnetic rods, and at least one flow limiting element. The magnetic rods include at least one first magnetic rod and at least one second magnetic rod. Inner elements of the first magnetic rod and the second magnetic rod are alternately positioned with opposite magnetic poles in the ferromagnetism casing. The at least one flow limiting element is arranged in at least one weak magnetic area in the ferromagnetism casing to prevent fluid from flowing through the at least one weak magnetic area. In addition, a fluid pipe magnetization device with the same is also disclosed herein.

Abstract: A non-diffusion type photodiode is described and has: a substrate, a buffer layer, a light absorption layer, an intermediate layer, and a multiplication/window layer. The buffer layer is disposed on the substrate. The light absorption layer is disposed on the buffer layer. The intermediate layer is disposed on the light absorption layer and has a first boundary, wherein the intermediate layer is an I-type semiconductor layer or a graded refractive index layer. The multiplication/window layer is disposed on the intermediate layer and has a second boundary, wherein in a top view, the first boundary surrounds the second boundary, and a distance between the first boundary and the second boundary is greater than or equal to 1 micrometer. The non-diffusion type photodiode can reduce generation of dark current.

Abstract: In an embodiment, a method includes: receiving, within a processing chamber, a wafer with a photoresist mask above a metal layer, wherein the processing chamber is connected to a gas source; applying an etchant configured to etch the metal layer in accordance with the photoresist mask within the processing chamber; and applying gas from the gas source to perform plasma ashing in the processing chamber.

Abstract: A method of biasing a guard ring structure includes biasing a gate of a MOS transistor to a first bias voltage level, biasing first and second S/D regions of the MOS transistor to a power domain voltage level, biasing a gate of the guard ring structure to a second bias voltage level, and biasing first and second heavily doped regions of the guard ring structure to the power domain voltage level. Each of the first and second S/D regions has a first doping type, each of the first and second heavily doped regions has a second doping type different from the first doping type, and each of the first and second S/D regions and the first and second heavily doped regions is positioned in a substrate region having the second doping type.

Abstract: A light-emitting device includes a circuit carrier board having a short side and a long side, a plurality of light-emitting units on the circuit carrier board for emitting three or more color lights, and a light-transmitting glue layer on the circuit carrier board and covering the plurality of light-emitting units. The short side is shorter than the long side. The plurality of light-emitting units include a first light-emitting unit. The first light-emitting unit has a light exit surface, a first sidewall, and a second sidewall. The first sidewall faces the short side and has a first included angle with the light exit surface, and the second sidewall faces the long side and has a second included angle with the light exit surface. The first included angle is between 85 to 95 degrees, and the second included angle is less than 85 degrees or greater than 105 degrees.

Abstract: A pixel package includes an electrode structure, a plurality of light-emitting units arranged on the electrode structure, and a light transmitting layer. The electrode structure has an upper layer with a first upper sheet, a lower layer with a first lower sheet, and a supporting layer arranged between the upper layer and the lower layer. The electrode structure and the plurality of light-emitting units are fully embedded in the light transmitting layer. In a top view of the pixel package, the first upper sheet is overlapped with and larger than the first lower sheet.

Abstract: The display device includes a first substrate; an active layer disposed on the first substrate; a first insulation layer disposed on the active layer; a first electrode layer disposed on the first insulation layer including a gate electrode line extending along a first direction and a protruding portion extending along a second direction; a second insulation layer disposed on the first electrode layer; and a second electrode layer disposed on the second insulation layer. The second electrode layer includes a date line extending along the second direction and a conductive layer. The conductive layer includes a first conductive portion and a second conductive portion, wherein the first conductive portion has a first maximum width A along the first direction, and the second conductive portion has a second maximum width B along the first direction. The first maximum width A is less than the second maximum width B.

Abstract: A device is provided. The device includes an operational amplifier, an output circuit, a first capacitor, and a second capacitor. The operational amplifier is configured to generate an output according to a feedback signal. The output circuit is configured to generate a first current signal in response to a supply voltage and the output of the operational amplifier. The first current signal includes a first ripple signal. The first capacitor and the second capacitor are coupled in parallel between the operational amplifier and the output circuit. The first capacitor is configured to receive the first current signal and feedback to the operational amplifier the first ripple signal.

Abstract: A light emitting device includes a substrate, a first group of light emitting diode (LED) structures, a second group of LED structures, and a connection port is provided. The substrate has a first surface and a second surface opposite to the first surface. The first group of LED structures is disposed on one side of the first surface. The second group of LED structures is disposed on another side of the first surface opposite to the first group of LED structures. The connection portion includes at least an opening, and a first connection pad and a second connection pad electrically coupled to at least a part of the LED structures. The connection port is adapted to be coupled to other device through the opening. A light emitting module and an illuminating apparatus are also provided.

Abstract: A safety gate is configured to be mounted at a gateway and has a frame and a gate body. The frame is configured to be mounted between two walls disposed at two sides of the gateway. The frame has two sides and two first positioning assemblies respectively disposed at the two sides of the frame. The gate body is disposed in the frame and has two sides and two first pivot assemblies respectively disposed at the two sides of the gate body. The first pivot assembly at each side of the gate body is configured to detachably and pivotally connect with the first positioning assembly at a respective one of the sides of the frame.

Abstract: An integrated circuit includes a first metal-insulator-semiconductor capacitor, a second metal-insulator-semiconductor capacitor, and a metal-insulator-metal capacitor. A first terminal of the first metal-insulator-semiconductor capacitor is configured to receive a first reference voltage for a higher voltage domain, while a first terminal of the second metal-insulator-semiconductor capacitor is configured to receive a second reference voltage for the higher voltage domain. A second terminal of the first metal-insulator-semiconductor capacitor is conductively connected to a first terminal of the metal-insulator-metal capacitor, while a second terminal of the second metal-insulator-semiconductor capacitor is conductively connected to a second terminal of the metal-insulator-metal capacitor.

Abstract: The optical device includes a first photodiode, a second photodiode, and a hybrid absorber. The hybrid absorber is disposed above the first photodiode and the second photodiode. The hybrid absorber includes a color filter layer and a plurality of metal-insulator-metal structures. The color filter layer includes a first color filter disposed on the first photodiode and a second color filter disposed on the second photodiode, in which the first color filter is different from the second color filter. The plurality of metal-insulator-metal structures are disposed above the first photodiode and free of disposed above the second photodiode.