Abstract: A method for processing a semiconductor device is provided. The semiconductor device includes a protruding structure on a substrate, the protruding structure having a nitride spacer at a sidewall, and an epitaxial layer is formed in the substrate adjacent to the protruding structure. The method includes removing the nitride spacer on the protruding structure. Then, a dilute hydrofluoric (DHF) cleaning process is performed over the substrate, wherein a top surficial portion of the epitaxial layer is removed. A standard clean (SC) process is performed over the substrate, wherein a native oxide layer is formed on an expose surface of the epitaxial layer.

Abstract: A method for virtual reality (VR) or augmented reality (AR) includes sensing a relative angle between a reference direction defined by a first tracking device and a navigate direction defined by a second tracking device, calculating a viewing angle according to the relative angle between the reference direction and the navigate direction, and displaying a VR or AR environment in the corresponding viewing angle.

Abstract: An actuator is provided, including a fixed assembly and a movable assembly. The fixed assembly includes a coil module, a base, a first screwing member, and a linear rail. The first screwing member passes through the base and the linear rail, and the linear rail is positioned on the base. The movable assembly includes a U-shaped back board having an inner space, a first magnetic module, a second magnetic module aligned with the first magnetic module, and a sliding block. The first and second magnetic modules are disposed on the U-shaped back board and accommodated in the inner space. The coil module is disposed between the first magnetic module and the second magnetic module. The sliding block is positioned on the U-shaped back board in the inner space, and slidably connected to the linear rail.

Abstract: A network of collection, charging and distribution machines collect, charge and distribute portable electrical energy storage devices (e.g., batteries, supercapacitors or ultracapacitors). Locations of collection, charging and distribution machines having available charged portable electrical energy storage devices are communicated to or acquired by a mobile device of a user or a navigation system of a user's vehicle. The locations are indicated on a graphical user interface on a map relative to the user's current location. The user may select particular locations on the map to reserve an available portable electrical energy storage device at a particular collection, charging and distribution machine location. The collection, charging and distribution machine locations displayed may also be based on a physical distance or driving time from the current location of the user mobile device or vehicle.

Abstract: A method of forming a gate structure on a fin structure includes the steps of providing a fin structure covered by a first silicon oxide layer, a silicon nitride layer, a gate material and a cap material in sequence, wherein the silicon nitride layer contacts the first silicon oxide layer. Later, the cap material is patterned to form a first cap layer and the gate material is patterned to form a first gate electrode by taking the silicon nitride layer as an etching stop layer. Then, the silicon nitride layer not covered by the first gate electrode is removed to expose part of the first silicon oxide layer. Finally, a first dielectric layer is formed to conformally cover the first silicon oxide layer, the first gate electrode and the first cap layer.

Abstract: A method includes forming a first conductive feature and a second conductive feature, forming a metal pad over and electrically connected to the first conductive feature, and forming a passivation layer covering edge portions of the metal pad, with a center portion of a top surface of the metal pad exposed through an opening in the metal pad. A first dielectric layer is formed to cover the metal pad and the passivation layer. A bond pad is formed over the first dielectric layer, and the bond pad is electrically coupled to the second conductive feature. A second dielectric layer is deposited to encircle the bond pad. A planarization is performed to level a top surface of the second dielectric layer with the bond pad. At a time after the planarization is performed, an entirety of the top surface of the metal pad is in contact with dielectric materials.

Abstract: A color filter array for an image sensing device includes a plurality of pixels, for generating a plurality of pixel data of an image; and a control unit, for controlling the plurality of pixels; wherein each of the plurality of pixels is divided into a plurality of sub-pixels; wherein the pixel data outputted by each of the plurality of pixels is generated based on at least one pixel value of the plurality of sub-pixels and the outputted pixel data is smaller than a saturated threshold; wherein at least one pixel in the plurality of pixels has a mixed color by having different sub-pixel colors in the plurality of sub-pixels.

Abstract: A method of forming a gate structure on a fin structure includes the steps of providing a fin structure covered by a first silicon oxide layer, a silicon nitride layer, a gate material and a cap material in sequence, wherein the silicon nitride layer contacts the first silicon oxide layer. Later, the cap material is patterned to form a first cap layer and the gate material is patterned to form a first gate electrode by taking the silicon nitride layer as an etching stop layer. Then, the silicon nitride layer not covered by the first gate electrode is removed to expose part of the first silicon oxide layer. Finally, a first dielectric layer is formed to conformally cover the first silicon oxide layer, the first gate electrode and the first cap layer.

Abstract: A method for fabricating a semiconductor device. A gate is formed on a substrate. A spacer is formed on each sidewall of the gate. A hard mask layer is formed on the spacer. A recessed region is formed in the substrate and adjacent to the hard mask layer. An epitaxial layer is formed in the recessed region. The substrate is subjected to an ion implantation process to bombard particle defects on the hard mask layer with inert gas ions. An annealing process is performed to repair damages to the epitaxial layer caused by the ion implantation process. The hard mask layer is then removed.

Abstract: The optical sensor device including a sensor layer, a microlens layer and a filter layer is provided. The sensor layer includes a plurality of sensor areas, and is configured to sense a multi-wavelength light from a finger. The microlens layer includes a plurality of microlenses arranged in an array, and is disposed on the sensor layer. Each of the microlenses focuses the multi-wavelength light on a corresponding one of the sensor areas. The filter layer is disposed between the sensor layer and the microlens layer, and configured to filter the multi-wavelength light to generate a plurality of lights with different wavelengths. In addition, the fingerprint sensor apparatus including the foregoing optical sensor device is also provided.

Abstract: A method for post chemical mechanical polishing clean is provided in the present invention, which include the steps of providing a substrate, performing a chemical mechanical polishing process, and performing a plurality of cleaning processes sequentially substrate using solutions of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) with different ratios and at different temperatures.

Abstract: A two-way distribution, charging, and vending system permits a subscriber to exchange one or more partially or completely discharged portable electric energy storage devices for a comparable number of charged portable electric energy storage devices. The two-way distribution, charging, and vending system includes a number of charging modules, each with a dedicated power converter, communicably coupled to at least one two-way distribution system controller and to a power distribution grid. Upon receipt of a discharged portable electric energy storage device, the at least one two-way distribution system controller validates a manufacturer identifier and a subscriber identifier stored in a nontransitory storage media carried by the discharged portable electric energy storage device. Responsive to a successful authentication and validation, the at least one two-way distribution system controller dispenses a charged portable electric energy storage device to the subscriber.

Abstract: A method for fabricating the semiconductor device is disclosed. A semiconductor substrate having a main surface is provided. A gate is formed on the main surface of the semiconductor substrate. An offset liner is formed on the sidewall of the gate. An ion implantation process is performed to form lightly doped drain (LDD) region in the semiconductor substrate. A spacer is formed on a sidewall of the gate. A cavity is recessed into the main surface of the semiconductor substrate. The cavity is adjacent to the spacer. An epitaxial layer is grown in the cavity. The spacer is then subjected to a surface treatment to form a dense oxide film on the spacer. A mask layer is deposited on the dense oxide film. The dense oxide film has a thickness that is smaller or equal to 12 angstroms.

Abstract: A method for virtual reality (VR) includes displaying a VR event in a view of a first VR position in a VR environment in a first period, wherein a user's VR avatar is at the first VR position in the first period; recording the VR event; and redisplaying the recorded VR event in a view of a second VR position in the VR environment in a second period.

Abstract: A method for fabricating a semiconductor device. A gate is formed on a substrate. A spacer is formed on each sidewall of the gate. A hard mask layer is formed on the spacer. A recessed region is formed in the substrate and adjacent to the hard mask layer. An epitaxial layer is formed in the recessed region. The substrate is subjected to an ion implantation process to bombard particle defects on the hard mask layer with inert gas ions. An annealing process is performed to repair damages to the epitaxial layer caused by the ion implantation process. The hard mask layer is then removed.

Abstract: A non-volatile memory having discrete isolation structures and SONOS (Silicon Oxide Nitride Oxide Silicon) memory cells, a method of operating the same, and a method of manufacturing the same are introduced. Every isolation structure on a semiconductor substrate having an array region has a plurality of gaps so as to form discrete isolation structures and thereby implant source lines in the gaps of the semiconductor substrate. Since the source lines are not severed by the isolation structures, the required quantity of barrier pins not connected to the source line is greatly reduced, thereby reducing the space required for the barrier pins in the non-volatile memory.

Abstract: Provided is a 3DIC structure includes a wafer, a die and a dielectric layer. The die is over and bonded to the wafer. The dielectric layer is over the wafer and aside the die, covering sidewalls of the die. A total thickness variation (TTV) of the die is less than 0.8 ?m.

Abstract: A method of manufacturing a semiconductor device includes: providing a substrate including a first semiconductive region of a first conductive type and gate structures over the first semiconductive region, where a gap between the gate structures exposes a portion of the first semiconductive region; and forming a second semiconductive region of a second conductive type in the gap starting from the exposed portion of the first semiconductive region. The forming of the second semiconductive region includes: growing, in a chamber, an epitaxial silicon-rich layer with a first growth rate around a sidewall adjacent to the gate structures that is greater than a second growth rate at a central portion; and, in the chamber, partially removing the epitaxial silicon-rich layer with an etchant with a first etching rate around the sidewall adjacent to the gate structures that is greater than a second etching rate at the central portion.

Abstract: Provided is a die stack structure including a first die, a second die, a first bonding structure, and a second bonding structure. The first bonding structure is disposed on a back side of the first die. The second bonding structure is disposed on a front side of the second die. The first die and the second die are bonded together via the first bonding structure and the second bonding structure and a bondable topography variation of a surface of the first bonding structure bonding with the second bonding structure is less than less than 1 ?m per 1 mm range. A method of manufacturing the die stack structure is also provided.

Abstract: A method of manufacturing a semiconductor package structure includes the following steps. A die is bonded to a wafer. A dielectric material layer is formed on the wafer and the die. The dielectric material layer covers a top surface and sidewalls of the die. At least one planarization process is performed to remove a portion of the dielectric material layer and a portion of the die, such that the top surface of the die is exposed and a dielectric layer aside the die is formed. The dielectric layer surrounds and covers the sidewalls of the die.