Abstract: A semiconductor arrangement includes an isolation structure having a first electrical insulator layer in a trench in a semiconductor substrate and a second electrical insulator layer in the trench and over the first electrical insulator layer.

Abstract: An under display light field sensor is for sensing a fingerprint or touch on or in proximity to a display panel. The under display light field sensor includes a light-field image sensor and a plurality of micro-lenses on the subarrays of the sensing pixels. The light-field image sensor includes a plurality of subarrays of sensing pixels under the display panel. The sensing pixels in an identical one of the subarrays are configured to capture images of an object on or in proximity to the display panel by sensing lights from different directions. Each of the micro-lenses corresponds to one of the subarrays of the sensing pixels.

Abstract: Methods of manufacturing a semiconductor package structure are provided. A method includes: bonding dies and dummy dies to a wafer; forming a dielectric material layer on the wafer to cover the dies and the dummy dies; performing a first planarization process to remove a first portion of the dielectric material layer over top surfaces of the dies and the dummy dies; and performing a second planarization process to remove portions of the dies, portions of the dummy dies and a second portion of the dielectric material layer, and a dielectric layer is formed laterally aside the dies and the dummy dies; wherein after the second planarization process is performed, a total thickness variation of the dies is less than a total thickness variation of the dummy dies.

Abstract: An actuator is provided, including a fixed assembly and a movable assembly. The fixed assembly includes a coil module, a base, a first screwing member, and a linear rail. The first screwing member passes through the base and the linear rail, and the linear rail is positioned on the base. The movable assembly includes a U-shaped back board having an inner space, a first magnetic module, a second magnetic module aligned with the first magnetic module, and a sliding block. The first and second magnetic modules are disposed on the U-shaped back board and accommodated in the inner space. The coil module is disposed between the first magnetic module and the second magnetic module. The sliding block is positioned on the U-shaped back board in the inner space, and slidably connected to the linear rail.

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure and an epitaxial structure. The gate structure is disposed on the substrate, and the epitaxial structure is disposed in the substrate, at one side of the gate structure. The epitaxial structure includes a portion being protruded from a top surface of the substrate, and the portion includes a discontinuous sidewall, with a distance between a turning point of the discontinuous sidewalls and the gate structure being a greatest distance between the epitaxial structure and the gate structure.

Abstract: A semiconductor processing system is provided to form a capacitor dielectric layer in a metal-insulator-metal capacitor. The semiconductor processing system includes a precursor tank configured to generate a precursor gas from a metal organic solid precursor, a processing chamber configured to perform a plasma enhanced chemical vapor deposition, and at least one buffer tank between the precursor tank and the processing chamber. The at least one buffer tank is coupled to the precursor tank via a first pipe and coupled to the processing chamber via a second pipe.

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure and an epitaxial structure. The gate structure is disposed on the substrate, and the epitaxial structure is disposed in the substrate, at one side of the gate structure. The epitaxial structure includes a portion being protruded from a top surface of the substrate, and the portion includes a discontinuous sidewall, with a distance between a turning point of the discontinuous sidewalls and the gate structure being a greatest distance between the epitaxial structure and the gate structure.

Abstract: A method of manufacturing a semiconductor package structure includes: bonding a die to a wafer; forming a dielectric material layer on the wafer to cover a top surface and sidewalls of the die; performing a removal process to remove a portion of the dielectric material layer, so as to at least expose a portion of the top surface of the die, wherein the dielectric material layer comprises a protruding part over the top surface of the die after performing the removal process; and performing a planarization process to planarize top surfaces of the die and the dielectric material layer, and thereby forming a dielectric layer laterally aside the die.

Abstract: A RRAM and its manufacturing method are provided. The RRAM includes an interlayer dielectric layer, a first bottom contact structure, and a second bottom contact structure formed on a substrate. A first memory cell is formed on the first bottom contact structure. The first memory cell includes a first bottom electrode layer which includes a first conductive region. A pattern in which the first conductive region is vertically projected on the first bottom contact structure is a first projection pattern. A second memory cell is formed on the second bottom contact structure. The second memory cell includes a second bottom electrode layer which includes a second conductive region. A pattern in which the second conductive region is vertically projected on the second bottom contact structure is a second projection pattern. The second projection pattern is different from the first projection pattern.

Abstract: A resistive random access memory (RRAM) device and a manufacturing method are provided. The RRAM device includes bottom electrodes, a resistance switching layer, insulating patterns, a channel layer and top electrodes. The resistance switching layer blanketly covers the bottom electrodes. The insulating patterns are disposed on the resistance layer and located in corresponding to locations of the bottom electrodes. The channel layer conformally covers the resistance switching layer and the insulating patterns. The channel layer has a plurality of channel regions. The channel regions are located on the resistance switching layer, and cover sidewalls of the insulating patterns. The top electrodes respectively cover at least two of the channel regions, and respectively located in corresponding to one of the insulating patterns, such that the at least two of the channel regions are located between one of the bottom electrodes and one of the top electrodes.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer and a second spacer around the gate structure; forming a recess adjacent to two sides of the second spacer; performing a cleaning process to trim the second spacer for forming a void between the first spacer and the substrate; and forming an epitaxial layer in the recess.

Abstract: A resistive random access memory structure includes a semiconductor substrate, a transistor, a bottom electrode, a plurality of top electrodes, and a resistive-switching layer. The transistor is disposed over the semiconductor substrate. The bottom electrode is disposed over the semiconductor substrate and is electrically connected to a drain region of the transistor. The plurality of top electrodes is disposed along a sidewall of the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the plurality of top electrodes.

Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided, in which the method includes the steps of forming a gate structure on a substrate, forming a spacer on a sidewall of the gate structure, forming two recesses adjacent to two sides of the spacer, performing a cleaning process to trim the spacer for forming a void between the spacer and the substrate, and forming two portions of an epitaxial layer in the two recesses. The semiconductor device preferably includes a cap layer on the two portions of the epitaxial layer as the cap layer includes a planar top surface and an inclined sidewall.

Abstract: A fingerprint identification device and a fingerprint identification method are provided. The fingerprint identification device includes a self-emitting display panel, a fingerprint sensor and a processor. The self-emitting display panel displays at least one light pattern in a sensing region. The fingerprint sensor senses a finger object located above the sensing region of the self-emitting display panel to generate a first fingerprint image and a second fingerprint image corresponding to the at least one light pattern. The processor is coupled to the fingerprint sensor. The processor determines whether the first fingerprint image and the second fingerprint image have opposite tones to identify the finger object is a real finger or a fake finger.

Abstract: Provided is a die stack structure including a first die, a second die, a first bonding structure, and a second bonding structure. The first bonding structure is disposed on a back side of the first die. The second bonding structure is disposed on a front side of the second die. The first die and the second die are bonded together via the first bonding structure and the second bonding structure and a bondable topography variation of a surface of the first bonding structure bonding with the second bonding structure is less than less than 1 ?m per 1 mm range. A method of manufacturing the die stack structure is also provided.

Abstract: A speaker includes a casing, a first diaphragm and a second diaphragm. The casing encloses a first sound chamber and a second sound chamber independent of each other. The casing has a dividing wall, and the dividing wall blocks between the first sound chamber and the second sound chamber. The first diaphragm is disposed in the first sound chamber, the second diaphragm is disposed in the second sound chamber, and the vibration frequency of the second diaphragm is higher than the vibration frequency of the first diaphragm.

Abstract: Provided is a die structure including a die, a bonding structure, and a protection structure. The die includes a substrate and a metal feature disposed over the substrate. The bonding structure is disposed over the die. The bonding structure includes a bonding dielectric layer and a bonding metal layer disposed in the bonding dielectric layer. The bonding metal layer is electrically connected to the metal feature of the die. The protection structure is disposed between a top portion of the bonding metal layer and a top portion of the bonding dielectric layer. A die stack structure and a method of fabricating the die structure are also provided.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes: providing a substrate including a first semiconductive region of a first conductive type and gate structures over the first semiconductive region, wherein a gap between the gate structures exposes a portion of the first semiconductive region; and forming a second semiconductive region of a second conductive type in the gap starting from the exposed portion of the first semiconductive region. The forming of the second semiconductive region includes: growing, in a chamber, an epitaxial silicon-rich layer having a first sidewall adjacent to the gate structures and a first central portion; and, in the chamber, shaping the epitaxial silicon-rich layer to form a second sidewall adjacent to the gate structures and a second central portion, wherein a first height difference between the first sidewall and the first central portion is greater than a second height difference between the second sidewall and the second central portion.

Abstract: A resistive random access memory structure includes a semiconductor substrate, a transistor, a bottom electrode, a plurality of top electrodes, and a resistive-switching layer. The transistor is disposed over the semiconductor substrate. The bottom electrode is disposed over the semiconductor substrate and is electrically connected to a drain region of the transistor. The plurality of top electrodes is disposed along a sidewall of the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the plurality of top electrodes.

Abstract: A beam alignment method for an antenna array is provided. In the method, a base station uses multi-modal beam patterns for transmitting several synchronization signals. User equipment scans the synchronization signals, determines a synchronization signal with the strongest received power and a receive beam direction corresponding thereto, and transmits an initial access message including index information indicating the strongest synchronization signal.