Patents by Inventor Hsiu Chen

Hsiu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200193120
    Abstract: A fingerprint identification apparatus for detecting a fingerprint image of a finger is provided. The fingerprint identification apparatus includes a display, an optical sensor, and a control device. The display is configured to emit light and has a fingerprint imaging area. The control device drives a region of the display at the periphery of the fingerprint imaging area to emit light to the finger when the finger touches the fingerprint imaging area, and the optical sensor is configured to receive light reflected from the finger touching the fingerprint imaging area to determine the fingerprint image of the finger.
    Type: Application
    Filed: December 12, 2018
    Publication date: June 18, 2020
    Applicant: Novatek Microelectronics Corp.
    Inventor: I-Hsiu Chen
  • Patent number: 10677490
    Abstract: A compensational control method includes the steps of: controlling a plurality of indoor air conditioning apparatuses to be in operation according to a target temperature; receiving continuously an operating parameter and an environmental datum from each of the indoor air conditioning apparatus; determining whether there is a specific indoor air conditioning apparatus that needs support; acquiring an adjacent indoor air conditioning apparatus which is influential for the specific indoor air conditioning apparatus according to an influence form which is previously built; establishing a supportive strategy according to a supportable operation capability of the adjacent indoor air conditioning apparatus; and adjusting the operating parameter of the adjacent indoor air conditioning apparatus according to the supportive strategy. Therefore, the adjacent indoor air conditioning apparatus is provided to improve an ambient temperature of an area where the specific indoor air conditioning apparatus is installed.
    Type: Grant
    Filed: January 13, 2018
    Date of Patent: June 9, 2020
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Tien-Szu Lo, Meng-Seng Chen, Hsiang-Pin Lee, Ying-Hsiu Chen
  • Publication number: 20200176306
    Abstract: Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) device with an impurity competing layer to absorb potential contamination metal particles during an annealing process, and the SOI structure thereof. In some embodiments, an impurity competing layer is formed on the dummy substrate. An insulation layer is formed over a support substrate. A front side of the dummy wafer is bonded to the insulation layer. An annealing process is performed and the impurity competing layer absorbs metal from an upper portion of the dummy substrate. Then, a majority portion of the dummy substrate is removed including the impurity competing layer, leaving a device layer of the dummy substrate on the insulation layer.
    Type: Application
    Filed: August 21, 2019
    Publication date: June 4, 2020
    Inventors: Yu-Hung Cheng, Pu-Fang Chen, Cheng-Ta Wu, Po-Jung Chiang, Ru-Liang Lee, Victor Y. Lu, Yen-Hsiu Chen, Yeur-Luen Tu, Yu-Lung Yeh, Shi-Chieh Lin
  • Patent number: 10672737
    Abstract: Provided is a 3DIC structure includes a wafer, a die and a dielectric layer. The die is over and bonded to the wafer. The dielectric layer is over the wafer and aside the die, covering sidewalls of the die. A total thickness variation (TTV) of the die is less than 0.8 ?m.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Hsiu Chen, Ebin Liao, Hong-Ye Shih, Wen-Chih Chiou, Jia-Ling Ko
  • Patent number: 10665582
    Abstract: A method of manufacturing a semiconductor package structure includes the following steps. A die is bonded to a wafer. A dielectric material layer is formed on the wafer and the die. The dielectric material layer covers a top surface and sidewalls of the die. At least one planarization process is performed to remove a portion of the dielectric material layer and a portion of the die, such that the top surface of the die is exposed and a dielectric layer aside the die is formed. The dielectric layer surrounds and covers the sidewalls of the die.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Hsiu Chen, Chen-Hua Yu, Ming-Fa Chen, Wen-Chih Chiou
  • Patent number: 10659574
    Abstract: An operating method of a communication device includes performing a scan procedure to receive a device name and an address of an external device; determining a connection interval corresponding to the external device according to one or more policies stored in the communication device under a condition that the device name and/or the address match the one or more policies; and building a connection with the external device according to the connection interval and the address of the external device, so that the communication device and the external device communicate corresponding to the connection interval.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: May 19, 2020
    Assignee: HTC Corporation
    Inventors: Kai-Hsiu Chen, Cheng-Kang Lin, Yao-Te Tsai
  • Publication number: 20200151483
    Abstract: An embodiment of the invention provides an optical device including a first substrate, a light source, a second substrate, an image capturing device, a lens module and a lens holder. The light source outputs a first light beam. The second substrate includes a first surface and a second surface opposite to the first surface and closer to the first substrate. A scattered light beam which is generated by the first light beam entering an object touching the first surface of the second substrate and scattered in the object is a second light beam. The image capturing device receives a third light beam. The third light beam is the second light beam normally incident to the second surface and transmitted to the image capturing device. The lens module focuses the third light beam to be captured by the image capturing device.
    Type: Application
    Filed: January 15, 2020
    Publication date: May 14, 2020
    Applicant: Novatek Microelectronics Corp.
    Inventors: Li-Yuan Chang, I-Hsiu Chen, Chin-Hui Huang
  • Publication number: 20200150404
    Abstract: An optical device including a first substrate, a light source, a second substrate, an image capturing device, a lens module and a lens holder is provided. The light source outputs a first light beam. The second substrate includes a first surface and a second surface opposite to the first surface and closer to the first substrate. A scattered light beam which is generated by the first light beam entering an object touching the first surface of the second substrate and scattered in the object is a second light beam. The image capturing device receives a third light beam. The third light beam is the second light beam normally incident to the second surface and transmitted to the image capturing device. The lens module focuses the third light beam to be captured by the image capturing device. The lens holder is located between the light source and the image capturing device.
    Type: Application
    Filed: January 15, 2020
    Publication date: May 14, 2020
    Applicant: Novatek Microelectronics Corp.
    Inventors: Li-Yuan Chang, I-Hsiu Chen, Chin-Hui Huang
  • Patent number: 10651174
    Abstract: A method of forming a gate structure on a fin structure includes the steps of providing a fin structure covered by a first silicon oxide layer, a silicon nitride layer, a gate material and a cap material in sequence, wherein the silicon nitride layer contacts the first silicon oxide layer. Later, the cap material is patterned to form a first cap layer and the gate material is patterned to form a first gate electrode by taking the silicon nitride layer as an etching stop layer. Then, the silicon nitride layer not covered by the first gate electrode is removed to expose part of the first silicon oxide layer. Finally, a first dielectric layer is formed to conformally cover the first silicon oxide layer, the first gate electrode and the first cap layer.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: May 12, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Liang Ye, Kuang-Hsiu Chen, Chun-Wei Yu, Chueh-Yang Liu, Yu-Ren Wang
  • Publication number: 20200144401
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes: providing a substrate including a first semiconductive region of a first conductive type and gate structures over the first semiconductive region, wherein a gap between the gate structures exposes a portion of the first semiconductive region; and forming a second semiconductive region of a second conductive type in the gap starting from the exposed portion of the first semiconductive region. The forming of the second semiconductive region includes: growing, in a chamber, an epitaxial silicon-rich layer having a first sidewall adjacent to the gate structures and a first central portion; and, in the chamber, shaping the epitaxial silicon-rich layer to form a second sidewall adjacent to the gate structures and a second central portion, wherein a first height difference between the first sidewall and the first central portion is greater than a second height difference between the second sidewall and the second central portion.
    Type: Application
    Filed: December 24, 2019
    Publication date: May 7, 2020
    Inventors: YU-HUNG CHENG, PO-JUNG CHIANG, YEN-HSIU CHEN, YEUR-LUEN TU
  • Publication number: 20200135922
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure and an epitaxial structure. The gate structure is disposed on the substrate, and the epitaxial structure is disposed in the substrate, at one side of the gate structure. The epitaxial structure includes a portion being protruded from a top surface of the substrate, and the portion includes a discontinuous sidewall, with a distance between a turning point of the discontinuous sidewalls and the gate structure being a greatest distance between the epitaxial structure and the gate structure.
    Type: Application
    Filed: November 30, 2018
    Publication date: April 30, 2020
    Inventors: Kuang-Hsiu Chen, Sung-Yuan Tsai, Chi-Hsuan Tang, Chun-Wei Yu, Yu-Ren Wang
  • Patent number: 10636842
    Abstract: A method for forming a resistive random access memory includes forming a layer stack, patterning the layer stack to form a plurality of stack structures, forming a protection layer along sidewalls of the plurality of stack structures, forming a first isolation structure between the plurality of stack structures, forming at least one recess in at least one stack structure to define a plurality of filament units, and forming a second isolation structure in the at least one recess. The layer stack includes a bottom electrode and a resistive switching layer on the bottom electrode.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: April 28, 2020
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Chia-Wen Cheng, Yi-Hsiu Chen, Po-Yen Hsu, Ping-Kun Wang, Ming-Che Lin, He-Hsuan Chao
  • Publication number: 20200118879
    Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a first semiconductor device and a second semiconductor device are formed within a semiconductor wafer and a scribe region between the first semiconductor device and the second semiconductor device is patterned. A singulation process is then utilized within the scribe region to singulate the first semiconductor device from the second semiconductor device. The first semiconductor device and the second semiconductor device are then bonded to a second semiconductor substrate and thinned in order to remove extension regions from the first semiconductor device and the second semiconductor device.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Inventors: Chen-Hua Yu, Hung-Pin Chang, Yi-Hsiu Chen, Ku-Feng Yang, Wen-Chih Chiou
  • Publication number: 20200098916
    Abstract: A semiconductor device is disclosed. The semiconductor device comprises a substrate, a gate structure disposed on the substrate, a spacer disposed on the substrate and covering a sidewall of the gate structure, an air gap sandwiched between the spacer and the substrate, and a source/drain region disposed in the substrate and having a faceted surface exposed from the substrate, wherein the faceted surface borders the substrate on a boundary between the air gap and the substrate.
    Type: Application
    Filed: October 28, 2018
    Publication date: March 26, 2020
    Inventors: Kuang-Hsiu Chen, Sung-Yuan Tsai, Chi-Hsuan Tang, Kai-Hsiang Wang, Chao-Nan Chen, Shi-You Liu, Chun-Wei Yu, Yu-Ren Wang
  • Patent number: 10600732
    Abstract: A structure of semiconductor device includes a substrate. An interconnection layer is formed on the substrate including a first inter-layer dielectric (ILD) layer over the substrate. A lower wiring structure is formed in the ILD layer. A hard mask layer is disposed on the first ILD layer. The hard mask layer has a first opening and a second opening being adjacent to expose the lower wiring structure. A second ILD layer is disposed on the hard mask layer. The second ILD layer has a via opening aligned to the first opening of the mask layer and a trench pattern connecting with the via opening. The second ILD layer has a protruding portion to fill the second opening of the mask layer. A metal line layer fills the via opening and the trench pattern in the second ILD layer and the first opening of the hard mask layer.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: March 24, 2020
    Assignee: United Microelectronics Corp.
    Inventors: Min-Shiang Hsu, Yu-Han Tsai, Yi-Hsiu Chen, Chih-Sheng Chang
  • Patent number: 10593877
    Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode over a substrate, a top electrode, a resistance-switching layer, an oxygen exchange layer, and a sidewall protective layer. The top electrode is disposed over the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The oxygen exchange layer is disposed between the resistance-switching layer and the top electrode. The sidewall protective layer containing metal or semiconductor is disposed at sidewalls of the resistance-switching layer, and the sidewalls of the resistance-switching layer is doped with the metal or semiconductor from the sidewall protective layer.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: March 17, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Frederick Chen, Ping-Kun Wang, Shao-Ching Liao, Po-Yen Hsu, Yi-Hsiu Chen, Ting-Ying Shen, Bo-Lun Wu, Meng-Hung Lin, Chia-Hua Ho, Ming-Che Lin
  • Publication number: 20200075480
    Abstract: A structure of semiconductor device includes a substrate. An interconnection layer is formed on the substrate including a first inter-layer dielectric (ILD) layer over the substrate. A lower wiring structure is formed in the ILD layer. A hard mask layer is disposed on the first ILD layer. The hard mask layer has a first opening and a second opening being adjacent to expose the lower wiring structure. A second ILD layer is disposed on the hard mask layer. The second ILD layer has a via opening aligned to the first opening of the mask layer and a trench pattern connecting with the via opening. The second ILD layer has a protruding portion to fill the second opening of the mask layer. A metal line layer fills the via opening and the trench pattern in the second ILD layer and the first opening of the hard mask layer.
    Type: Application
    Filed: September 5, 2018
    Publication date: March 5, 2020
    Applicant: United Microelectronics Corp.
    Inventors: Min-Shiang Hsu, Yu-Han Tsai, Yi-Hsiu Chen, Chih-Sheng Chang
  • Patent number: 10539765
    Abstract: An optical device including a first substrate, a light source, a second substrate, an image capturing device, a microstructure layer, and an infrared pass layer is provided. The light source is disposed on the first substrate. The second substrate is disposed above the first substrate. The second substrate includes a first surface and a second surface opposite to the first surface. The image capturing device is disposed on the first substrate to receive a light beam, which is originated from scattered light beams scattered by an object touching the first surface of the second substrate. The microstructure layer is disposed on the first surface of the second substrate. The microstructure layer is adapted to increase a light beam, which is scattered by the object and transmitted to the image capturing device. The infrared pass layer is adapted to pass the infrared light.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: January 21, 2020
    Assignee: Novatek Microelectronics Corp.
    Inventors: Li-Yuan Chang, I-Hsiu Chen, Chin-Hui Huang
  • Patent number: 10533847
    Abstract: An inspection mechanism for metal blank, adapted for sensing the surface condition of a metal blank, includes a framework, a holding device, a shuffling device, and an inductive control device. It mainly utilizes the inductive control device to drive the holding device to hold and position the metal blank and control the shuffling device to move the sensor of the inductive control device to the path of sensing the metal blank, so as to conduct the sensing operation.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: January 14, 2020
    Assignee: FACTORY AUTOMATION TECHNOLOGY CO., LTD.
    Inventors: Po Cheng Su, Hsin Hong Hou, Kuo Hsiu Chen, Shun Yu Yang
  • Patent number: 10532667
    Abstract: A two-way distribution, charging, and vending system permits a subscriber to exchange one or more partially or completely discharged portable electric energy storage devices for a comparable number of charged portable electric energy storage devices. The two-way distribution, charging, and vending system includes a number of charging modules, each with a dedicated power converter, communicably coupled to at least one two-way distribution system controller and to a power distribution grid. Upon receipt of a discharged portable electric energy storage device, the at least one two-way distribution system controller validates a manufacturer identifier and a subscriber identifier stored in a nontransitory storage media carried by the discharged portable electric energy storage device. Responsive to a successful authentication and validation, the at least one two-way distribution system controller dispenses a charged portable electric energy storage device to the subscriber.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: January 14, 2020
    Assignee: Gogoro Inc.
    Inventors: Jung-Hsiu Chen, Shen-Chi Chen, Yu-Lin Wu, Chien-Ming Huang, TsungTing Chan, Feng Kai Yang