Patents by Inventor Hsiu Chen

Hsiu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11502131
    Abstract: A resistive random access memory (RRAM) device and a manufacturing method are provided. The RRAM device includes bottom electrodes, a resistance switching layer, insulating patterns, a channel layer and top electrodes. The resistance switching layer blanketly covers the bottom electrodes. The insulating patterns are disposed on the resistance layer and located in corresponding to locations of the bottom electrodes. The channel layer conformally covers the resistance switching layer and the insulating patterns. The channel layer has a plurality of channel regions. The channel regions are located on the resistance switching layer, and cover sidewalls of the insulating patterns. The top electrodes respectively cover at least two of the channel regions, and respectively located in corresponding to one of the insulating patterns, such that the at least two of the channel regions are located between one of the bottom electrodes and one of the top electrodes.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: November 15, 2022
    Assignee: Winbond Electronics Corp.
    Inventors: Chia-Wen Cheng, Ping-Kun Wang, Yi-Hsiu Chen, He-Hsuan Chao
  • Publication number: 20220359689
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a channel structure extending between a first source/drain region and a second source/drain region. Further, a gate electrode is arranged directly over the channel structures, and an upper interconnect contact is arranged over and coupled to the gate electrode. A backside contact is arranged below and coupled to the first source/drain region. The backside contact has a width that decreases from a bottommost surface of the backside contact to a topmost surface of the backside contact.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: Yi-Hsiu Chen, Andrew Joseph Kelly
  • Patent number: 11447072
    Abstract: A multifunctional rearview mirror includes a casing having first and second receiving spaces. A mirror is mounted to one side of the casing that is formed with the first receiving space. The second receiving space is located under the first receiving space and has a front surface formed with first through-holes. A distance detection and alarm unit is arranged in the second receiving space and includes an ultrasonic distance detection module, an alarm light module, and a buzzer. The ultrasonic distance detection module is eclectically connected with the alarm light module and the buzzer. The alarm light module is arranged in the first through-holes. The ultrasonic distance detection module emits an ultrasonic wave, which is returned to the ultrasonic distance detection module by an object, so that a distance to the object is calculated and the alarm light module and the buzzer are activated according to the distance.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: September 20, 2022
    Inventor: Chi-Hsiu Chen
  • Publication number: 20220283449
    Abstract: Disclosed is a contact lens comprising an optical region including a first area, a second area and a third area, concentrically arranged in such order from a lens center. The first area includes a correction zone having a nearsightedness correcting power. The second and third areas each include at least two defocusing zones and at least one correction zone, wherein the at least two defocusing zones and the at least one correction zone are alternatively arranged. The second area has a first power difference of ?2.00 to ?5.00 D, the third area has a second power difference of ?3.00 to ?10.00 D, and the second power difference is equal to or more negative than the first power difference.
    Type: Application
    Filed: March 2, 2022
    Publication date: September 8, 2022
    Inventors: TSUNG-MIN TSAI, CHIEH-KAI WANG, CHIEN-HSIU CHEN
  • Patent number: 11437480
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a channel structure extending between a first source/drain region and a second source/drain region. Further, a gate electrode is arranged directly over the channel structures, and an upper interconnect contact is arranged over and coupled to the gate electrode. A backside contact is arranged below and coupled to the first source/drain region. The backside contact has a width that decreases from a bottommost surface of the backside contact to a topmost surface of the backside contact.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: September 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Hsiu Chen, Andrew Joseph Kelly
  • Publication number: 20220262698
    Abstract: A method includes forming a first passivation layer, forming a metal pad over the first passivation layer, forming a planarization layer having a planar top surface over the metal pad, and patterning the planarization layer to form a first opening. A top surface of the metal pad is revealed through the first opening. The method further includes forming a polymer layer extending into the first opening, and patterning the polymer layer to form a second opening. The top surface of the metal pad is revealed through the second opening.
    Type: Application
    Filed: May 19, 2021
    Publication date: August 18, 2022
    Inventors: Yi-Hsiu Chen, Wen-Chih Chiou, Chen-Hua Yu
  • Publication number: 20220231173
    Abstract: A semiconductor device and a method of forming the same is disclosed. The semiconductor device includes a substrate, a first well region disposed within the substrate, a second well region disposed adjacent to the first well region and within the substrate, and an array of well regions disposed within the first well region. The first well region includes a first type of dopants, the second well region includes a second type of dopants that is different from the first type of dopants, and the array of well regions include the second type of dopants. The semiconductor device further includes a metal silicide layer disposed on the array of well regions and within the substrate, a metal silicide nitride layer disposed on the metal silicide layer and within the substrate, and a contact structure disposed on the metal silicide nitride layer.
    Type: Application
    Filed: November 18, 2021
    Publication date: July 21, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ting-Ying WU, Yung-Hsiang CHEN, Yu-Lung YEH, Yen-Hsiu CHEN, Wei-Liang CHEN, Ying-Tsang HO
  • Publication number: 20220178992
    Abstract: A method of copper hillock detecting includes the following steps. A testkey structure is disposed on a substrate, wherein the testkey structure includes a lower metallization layer, an upper metallization layer, and a dielectric layer between the lower metallization layer and the upper metallization layer. A force voltage difference is applied to the lower metallization layer and the upper metallization layer under a test temperature and stress time. A changed sensing voltage difference to the lower metallization layer and the upper metallization layer is detected for detecting copper hillock.
    Type: Application
    Filed: December 8, 2020
    Publication date: June 9, 2022
    Inventors: Ching-Chih Chang, Yi-Hsiu Chen, Yuan-Fu Ko, Chih-Sheng Chang
  • Publication number: 20220157956
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a channel structure extending between a first source/drain region and a second source/drain region. Further, a gate electrode is arranged directly over the channel structures, and an upper interconnect contact is arranged over and coupled to the gate electrode. A backside contact is arranged below and coupled to the first source/drain region. The backside contact has a width that decreases from a bottommost surface of the backside contact to a topmost surface of the backside contact.
    Type: Application
    Filed: November 13, 2020
    Publication date: May 19, 2022
    Inventors: Yi-Hsiu Chen, Andrew Joseph Kelly
  • Publication number: 20220139769
    Abstract: Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) device with an impurity competing layer to absorb potential contamination metal particles during an annealing process, and the SOI structure thereof. In some embodiments, an impurity competing layer is formed on the dummy substrate. An insulation layer is formed over a support substrate. A front side of the dummy wafer is bonded to the insulation layer. An annealing process is performed and the impurity competing layer absorbs metal from an upper portion of the dummy substrate. Then, a majority portion of the dummy substrate is removed including the impurity competing layer, leaving a device layer of the dummy substrate on the insulation layer.
    Type: Application
    Filed: January 19, 2022
    Publication date: May 5, 2022
    Inventors: Yu-Hung Cheng, Pu-Fang Chen, Cheng-Ta Wu, Po-Jung Chiang, Ru-Liang Lee, Victor Y. Lu, Yen-Hsiu Chen, Yeur-Luen Tu, Yu-Lung Yeh, Shi-Chieh Lin
  • Publication number: 20220130169
    Abstract: A sensing device includes a light-field image sensor and a sensing circuit. The light-field image sensor includes a plurality of subarrays. One of the subarrays corresponds to sensing pixels. The sensing pixels are to capture images of an object on or in proximity to a display panel by sensing lights from different directions. The sensing circuit is to generate a plurality of sub-images of the object according to sensing signals of the sensing pixels and shift each of the sub-images of the object by an off-set to generate an image data.
    Type: Application
    Filed: January 3, 2022
    Publication date: April 28, 2022
    Inventors: I-Hsiu CHEN, Ching-Kuan CHIU
  • Publication number: 20220106012
    Abstract: A harmonic deceleration module, a dynamic power device, an automatic mobile vehicle, a transfer apparatus, a dynamic power supply system, and an electric bicycle are provided. The harmonic deceleration module includes a connecting member, a flexible bearing, a first frame, a first circular spline, a second frame, and a second circular spline. When the connecting member is driven, the connecting member rotates around a central axis. The connecting member has a cam part, and the cam part and the flexible bearing jointly form a wave generator. The wave generator is configured to be driven by the connecting member to drive a flexspline to continually and flexibly deform, and the flexspline drives the second circular spline and the second frame connected to the second circular spline to rotate. The second frame has a hollow channel penetrating through the second frame along the central axis.
    Type: Application
    Filed: October 4, 2021
    Publication date: April 7, 2022
    Inventors: KUN-JU HSIEH, CHANG-LIN LEE, TUNG-YU LI, CHING-HUEI WU, HSIU-CHEN TANG
  • Patent number: 11294152
    Abstract: An optical device including a first substrate, a light source, a second substrate, an image capturing device, a lens module and a lens holder is provided. The light source outputs a first light beam. The second substrate includes a first surface and a second surface opposite to the first surface and closer to the first substrate. A scattered light beam which is generated by the first light beam entering an object touching the first surface of the second substrate and scattered in the object is a second light beam. The image capturing device receives a third light beam. The third light beam is the second light beam normally incident to the second surface and transmitted to the image capturing device. The lens module focuses the third light beam to be captured by the image capturing device. The lens holder is located between the light source and the image capturing device.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: April 5, 2022
    Assignee: Novatek Microelectronics Corp.
    Inventors: Li-Yuan Chang, I-Hsiu Chen, Chin-Hui Huang
  • Patent number: 11250235
    Abstract: An under display light field sensor is for sensing a fingerprint or touch on or in proximity to a display panel. The under display light field sensor includes a light-field image sensor and a plurality of micro-lenses on the subarrays of the sensing pixels. The light-field image sensor includes a plurality of subarrays of sensing pixels under the display panel. The sensing pixels in an identical one of the subarrays are configured to capture images of an object on or in proximity to the display panel by sensing lights from different directions. Each of the micro-lenses corresponds to one of the subarrays of the sensing pixels.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: February 15, 2022
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: I-Hsiu Chen, Ching-Kuan Chiu
  • Publication number: 20220032845
    Abstract: A multifunctional rearview mirror includes a casing having first and second receiving spaces. A mirror is mounted to one side of the casing that is formed with the first receiving space. The second receiving space is located under the first receiving space and has a front surface formed with first through-holes. A distance detection and alarm unit is arranged in the second receiving space and includes an ultrasonic distance detection module, an alarm light module, and a buzzer. The ultrasonic distance detection module is eclectically connected with the alarm light module and the buzzer. The alarm light module is arranged in the first through-holes. The ultrasonic distance detection module emits an ultrasonic wave, which is returned to the ultrasonic distance detection module by an object, so that a distance to the object is calculated and the alarm light module and the buzzer are activated according to the distance.
    Type: Application
    Filed: July 30, 2020
    Publication date: February 3, 2022
    Inventor: Chi-Hsiu Chen
  • Patent number: 11232974
    Abstract: Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) device with an impurity competing layer to absorb potential contamination metal particles during an annealing process, and the SOI structure thereof. In some embodiments, an impurity competing layer is formed on the dummy substrate. An insulation layer is formed over a support substrate. A front side of the dummy wafer is bonded to the insulation layer. An annealing process is performed and the impurity competing layer absorbs metal from an upper portion of the dummy substrate. Then, a majority portion of the dummy substrate is removed including the impurity competing layer, leaving a device layer of the dummy substrate on the insulation layer.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: January 25, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Cheng, Pu-Fang Chen, Cheng-Ta Wu, Po-Jung Chiang, Ru-Liang Lee, Victor Y. Lu, Yen-Hsiu Chen, Yeur-Luen Tu, Yu-Lung Yeh, Shi-Chieh Lin
  • Patent number: 11227141
    Abstract: A fingerprint identification device and a fingerprint identification method are provided. The fingerprint identification device includes a self-emitting display panel, a fingerprint sensor and a processor. The self-emitting display panel displays at least one light pattern in a sensing region. The fingerprint sensor senses a finger object located above the sensing region of the self-emitting display panel to generate a first fingerprint image and a second fingerprint image corresponding to the at least one light pattern. The processor is coupled to the fingerprint sensor. The processor determines whether the first fingerprint image and the second fingerprint image have opposite tones to identify the finger object is a real finger or a fake finger.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: January 18, 2022
    Assignee: Novatek Microelectronics Corp.
    Inventors: Shao-Yang Chiang, I-Hsiu Chen, Hung-Yu Yang
  • Patent number: 11195905
    Abstract: A metal-oxide-semiconductor (MOS) transistor includes a substrate. The substrate has a plurality of trenches extending along a first direction and located on a top portion of the substrate. A gate structure line is located on the substrate and extends along a second direction intersecting with the first direction and crossing over the trenches. A first doped line is located in the substrate, located at a first side of the gate structure line, and crosses over the trenches. A second doped line is located in the substrate, located at a second side of the gate structure line, and crosses over the trenches.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: December 7, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsiang-Hua Hsu, Liang-An Huang, Sheng-Chen Chung, Chen-An Kuo, Chiu-Te Lee, Chih-Chung Wang, Kuang-Hsiu Chen, Ke-Feng Lin, Yan-Huei Li, Kai-Ting Hu
  • Publication number: 20210366954
    Abstract: A semiconductor device is provided. The semiconductor device includes a first deep trench isolation (DTI) structure within a substrate. The first DTI structure includes a barrier structure, a dielectric structure, and a copper structure. The dielectric structure is between the barrier structure and the copper structure. The barrier structure is between the substrate and the dielectric structure.
    Type: Application
    Filed: March 4, 2021
    Publication date: November 25, 2021
    Inventors: Yung-Hsiang CHEN, Yu-Lung YEH, Yen-Hsiu CHEN, Bo-Chang SU, Cheng-Hsien CHEN
  • Publication number: 20210353137
    Abstract: A device for simply determining maximum permissible exposure time (MPE) of retina is disclosed, which principally comprises a light receiving unit and a core processor that is provided with a color temperature determining unit, a luminous flux determining unit and a calculating unit therein. The color temperature determining unit and the luminous flux determining unit are configured for completing a color temperature determination and a luminous flux determination of a light provided by a light source, respectively. The calculating unit is configured for calculating a maximum permissible exposure time (MPE) of retina of the light source based on a use distance and a color temperature and a luminous flux of the light. By using this device, generic users are facilitated to achieve the calculation of any one kind of light's MPE by themselves, without needing to using any spectrometer.
    Type: Application
    Filed: September 22, 2020
    Publication date: November 18, 2021
    Inventors: JWO-HUEI JOU, JING-HSIU CHEN