Abstract: A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.

Abstract: Embodiments provide a method for forming a semiconductor device structure, includes forming a fin structure having first semiconductor layers and second semiconductor layers alternatingly stacked thereover, forming a sacrificial gate structure over a portion of the fin structure, removing portions of the sacrificial gate structure to expose the first and second semiconductor layers, removing portions of the second semiconductor layers to expose portions of each of the first semiconductor layers. The method includes surrounding the exposed portions of each of the first semiconductor layers with a cladding layer, wherein the cladding layer is formed of a material chemically different from the first semiconductor layers, and the cladding layer has a first atomic percentage of germanium.

Abstract: A method of forming a semiconductor device structure is provided. The method includes forming a plurality of dummy gates over a substrate and performing a first etch step and a second etch step on the substrate exposed between the dummy gates. The first etch step includes an anisotropic etching process and an isotropic etching process. The second includes an isotropic etching step.

Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. The via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. The first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. The via bulk layer can include tungsten and/or cobalt. A capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. In some implementations, the capping layer includes cobalt and silicon.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a gate structure formed over a substrate, and a first source/drain (S/D) structure formed adjacent to the gate structure. The semiconductor structure includes an S/D contact structure formed over the first S/D structure, and a dielectric wall formed below the gate structure and the S/D contact structure. The dielectric wall has a first portion directly below the S/D contact structure and a second portion directly below the gate structure, the first portion has a first height along a vertical direction, the second portion has a second height along the vertical direction, and the first height is smaller than the second height.

Abstract: A method includes forming a semiconductor fin over a substrate; forming isolation structures laterally surrounding the semiconductor fin; forming a gate structure over the semiconductor fin; forming a first spacer layer and a second spacer layer over the gate structure and the semiconductor fin; etching back the second spacer layer, such that a top surface of the second spacer layer is lower than a top surface of the first spacer layer; after etching back the second spacer layer, forming a third spacer layer over the first spacer layer and the second spacer layer; etching the first, second, and third spacer layers and the semiconductor fin to form recesses; and forming epitaxial source/drain structures in the recesses.

Abstract: A method for controlling an electric drive system, includes: determining that the vehicle is in a traveling condition; obtaining a rotation speed value, a shaft end torque value, a present direct axis current value, and a present quadrature axis current value of the motor when receiving a vehicle heat-up demand signal; determining a target torque curve according to the shaft end torque value, and determining a target traveling heating calibration curve according to the vehicle heat-up demand signal and the rotation speed value; determining an intersection of the target torque curve and the target traveling heating calibration curve as a target traveling condition point; determining a target quadrature axis current value and a target direct axis current value according to the target traveling condition point; and controlling, according to the target direct axis current value and the target quadrature axis current value, the motor to operate.

Abstract: Nucleic acid vectors encoding light-gated cation-selective membrane channels, in particular channelrhodopsin-2 (Chop2), converted inner retinal neurons to photosensitive cells in photoreceptor-degenerated retina in an animal model. Such treatment restored visual perception and various aspects of vision. A method of restoring light sensitivity to a retina of a subject suffering from vision loss due to photoreceptor degeneration, as in retinitis pigmentosa or macular degeneration, is provided. The method comprises delivering to the subject by intravitreal or subretinal injection, the above nucleic acid vector which comprises an open reading frame encoding a rhodopsin, to which is operatively linked a promoter and transcriptional regulatory sequences, so that the nucleic acid is expressed in inner retinal neurons.

Abstract: A transmission board includes: an insulating carrier; a pair of differential channels, including a first channel and a second channel; and a grounding structure, provided in the insulating carrier. An inner side of the first channel and an inner side of the second channel are separated from and coupled to each other. The first channel has a timing compensation section and a connecting section connected to the timing compensation section. A distance between an inner side of the timing compensation section and the inner side of the second channel is defined as a first distance. A distance between an inner side of the connecting section and the inner side of the second channel is defined as a second distance. The first distance is greater than the second distance. The grounding structure is located between the inner side of the timing compensation section and the inner side of the second channel.

Abstract: Structures and methods for the co-optimization of various device types include performing a first photolithography and etch process to simultaneously form a first source/drain recess for a first device in a first substrate region and a third source/drain recess for a third device in a third substrate region different than the first substrate region. In some embodiments, the method further includes performing a second photolithography and etch process to form a second source/drain recess for a second device in a second substrate region different than the first and third substrate regions. The method further includes forming a first source/drain feature within the first source/drain recess, a second source/drain feature within the second source/drain recess, and a third source/drain feature within the third source/drain recess.

Abstract: Transistors of different types of electronic devices on the same semiconductor substrate are configured with different transistor attributes to increase the performance of the different types of electronic devices. Fin height, shallow source drain (SSD) height, source or drain width, and/or one or more other transistor attributes may be co-optimized for the different types of electronic devices by various semiconductor manufacturing processes such as etching, lithography, process loading, and/or masking, among other examples. This enables the performance of a plurality of types of electronic devices on the same semiconductor substrate to be increased.

Abstract: In a power battery heating method for a vehicle, when a current temperature value of a power battery is lower than a preset temperature value, and a heating condition of the power battery meets a preset condition, a three-phase inverter is controlled to cause a three-phase alternating current motor to generate heat according to heating energy, to heat a coolant flowing through the power battery, a preset quadrature-axis current that causes a torque value outputted by the motor to be an appropriate value is obtained, and a corresponding preset direct-axis current is obtained according to heating power of the power battery, so as to control, according to the preset direct-axis current and the preset quadrature-axis current, the three-phase inverter to adjust a phase current of the three-phase alternating current motor in the heating process, where a direction of the preset direct-axis current changes periodically in the heating process.

Abstract: A motor control circuit includes a first switch module, a three-phase inverter, and a control module, where a power supply module, the first switch module, the three-phase inverter, and a three-phase alternating current motor form a current loop, the three-phase alternating current motor inputs or outputs a current by using a wire N extending from a connection point of three phase coils, and the control module controls the three-phase inverter, so that the motor control circuit receives a voltage of the power supply module and outputs a direct current. A wire N extends from the three-phase alternating current motor, and further forms different charging loops with the three-phase inverter, the three-phase alternating current motor, and the power battery.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming first and second semiconductor fins; forming first and second gate structures respectively over first regions of the first and second semiconductor fins; forming a first dummy spacer at a sidewall of the first gate structure adjacent a second region of the first semiconductor fin; etching a first source/drain recess in the second region of the first semiconductor fin; forming a n-type source/drain epitaxial structure in the first source/drain recess; forming a second dummy spacer at a sidewall of the second gate structure adjacent a second region of the second semiconductor fin, wherein the second dummy spacer has a thickness less than that of the first dummy spacer; etching a second source/drain recess in the second region of the second semiconductor fin; and forming a p-type source/drain epitaxial structure in the second source/drain recess.

Abstract: Structures and formation methods of a semiconductor device are provided. The method includes forming a first dummy gate structure across a first fin in a first transistor region of a semiconductor substrate and a second dummy gate structure across a second fin in a second transistor region of the semiconductor substrate. The method also includes selectively introducing atomic or ionic species into the second fin on opposite sides of the second dummy gate structure and etching portions of the first and second fins, so as to form first and second recesses. Each recess is in the respective fin on a side of the respective dummy gate structure. The first recess has a different depth than the second recess. The method further includes forming first and second source/drain features in the first and second recesses, respectively.

Abstract: A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack over a substrate. The first gate stack includes a first gate electrode and a dielectric layer between the first gate electrode and the substrate, and the first gate electrode has a void. The method includes oxidizing a side portion of the first gate electrode to form an oxide layer over the first gate electrode. The oxide layer fills the void.

Abstract: A dummy fin described herein includes a low dielectric constant (low-k or LK) material outer shell. A leakage path that would otherwise occur due to a void being formed in the low-k material outer shell is filled with a high dielectric constant (high-k or HK) material inner core. This increases the effectiveness of the dummy fin to provide electrical isolation and increases device performance of a semiconductor device in which the dummy fin is included. Moreover, the dummy fin described herein may not suffer from bending issues experienced in other types of dummy fins, which may otherwise cause high-k induced alternating current (AC) performance degradation. The processes for forming the dummy fins described herein are compatible with other fin field effect transistor (finFET) formation processes and are be easily integrated to minimize and/or prevent polishing issues, etch back issues, and/or other types of semiconductor processing issues.

Abstract: An embodiment method includes forming a semiconductor liner layer on a first fin structure and on a second fin structure and forming a first capping layer on the semiconductor liner layer disposed on the first fin structure. The method further includes forming a second capping layer on the semiconductor liner layer disposed on the first fin structure, where a composition of the first capping layer is different from a composition of the second capping layer. The method additionally includes performing a thermal process on the first capping layer, the second capping layer, and the semiconductor liner layer to form a first channel region in the first fin structure and a second channel region in the second fin structure. A concentration profile of a material of the first channel region is different from a concentration profile of a material of the second channel region.

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes first and second fins formed on a semiconductor substrate and laterally separated from each other by an isolation feature, the isolation feature formed of a dielectric material that physically contacts the semiconductor substrate; and a contact feature between the first and second fins and extending into the isolation feature thereby defining an air gap vertically between the isolation feature and the contact feature, the dielectric material of the isolation feature extending from the semiconductor substrate to the contact feature.