Patents by Inventor Hua Pan

Hua Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • 4,9-dioxo-4,9-dihydronaphtho[2,3-b]furan-3-carboxamide derivatives and uses thereof for treating proliferative diseases and infectious diseases
    Patent number: 11434229
    Abstract: The present disclosure provides compounds of Formulas (I), (II), and pharmaceutically acceptable salts thereof. The compounds described herein are useful in treating proliferative diseases, for example, cancer (e.g., lung cancer), and infectious diseases (e.g., bacterial infections).
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: September 6, 2022
    Assignees: Academia Sinica, National Taiwan UJniversity
    Inventors: Chi-Huey Wong, Pan-Chyr Yang, Rong-Jie Chein, Szu-Hua Pan, Ting-Jen R. Cheng
  • SEMICONDUCTOR DEVICE
    Publication number: 20220278102
    Abstract: Provided is a semiconductor device including a substrate, one hybrid fin, a gate, and a dielectric structure. The substrate includes at least two fins. The hybrid fin is disposed between the at least two fins. The gate covers portions of the at least two fins and the hybrid fin. The dielectric structure lands on the hybrid fin to divide the gate into two segment. The two segments are electrically isolated to each other by the dielectric structure and the hybrid fin. The hybrid fin includes a first portion, disposed between the two segments of the gate; and a second portion, disposed aside the first portion, wherein a top surface of the second portion is lower than a top surface of the first portion.
    Type: Application
    Filed: May 23, 2022
    Publication date: September 1, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-San Chien, Chun-Sheng Liang, Jhon-Jhy Liaw, Kuo-Hua Pan, Hsin-Che Chiang
  • Epitaxial Blocking Layer for Multi-Gate Devices and Fabrication Methods Thereof
    Publication number: 20220254623
    Abstract: A semiconductor device includes a semiconductor substrate having a first lattice constant, a dopant blocking layer disposed over the semiconductor substrate, the dopant blocking layer having a second lattice constant different from the first lattice constant, and a buffer layer disposed over the dopant blocking layer, the buffer layer having a third lattice constant different from the second lattice constant. The semiconductor device also includes a plurality of channel members suspended over the buffer layer, an epitaxial feature abutting the channel members, and a gate structure wrapping each of the channel members.
    Type: Application
    Filed: April 25, 2022
    Publication date: August 11, 2022
    Inventors: Hsin-Che Chiang, Wei-Chih Kao, Chun-Sheng Liang, Kuo-Hua Pan
  • Isolation Structure For Preventing Unintentional Merging Of Epitaxially Grown Source/Drain
    Publication number: 20220246613
    Abstract: A semiconductor device includes a first active region and a second active region disposed over a substrate. A first source/drain component is grown on the first active region. A second source/drain component is grown on the second active region. An interlayer dielectric (ILD) is disposed around the first source/drain component and the second source/drain component. An isolation structure extends vertically through the ILD. The isolation structure separates the first source/drain component from the second source/drain component.
    Type: Application
    Filed: April 25, 2022
    Publication date: August 4, 2022
    Inventors: Ta-Chun Lin, Kuan-Lin Yeh, Chun-Jun Lin, Kuo-Hua Pan, Mu-Chi Chiang
  • Vias for cobalt-based interconnects and methods of fabrication thereof
    Patent number: 11404309
    Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. The via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. The first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. The via bulk layer can include tungsten and/or cobalt. A capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. In some implementations, the capping layer includes cobalt and silicon.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Jen Chang, Min-Yann Hsieh, Hua Feng Chen, Kuo-Hua Pan
  • Semiconductor Devices Having Gate Dielectric Layers of Varying Thicknesses and Methods of Forming the Same
    Publication number: 20220238519
    Abstract: A method includes forming a first channel region, a second channel region, and a third channel region over a substrate, depositing a first interfacial layer over the first, second, and third channel regions, removing the first interfacial layer from the first and second channel regions, depositing a second interfacial layer over the first and second channel regions, thinning a thickness of the second interfacial layer over the first channel region, depositing a high-k dielectric layer over the first, second, and third channel regions, and forming a gate electrode layer over the first, second, and third channel regions.
    Type: Application
    Filed: April 11, 2022
    Publication date: July 28, 2022
    Inventors: Ta-Chun Lin, Kuo-Hua Pan, Jhon Jhy Liaw, Shien-Yang Wu
  • Semiconductor Device Structure With Uniform Threshold Voltage Distribution and Method of Forming the Same
    Publication number: 20220216329
    Abstract: An embodiment method includes: forming a semiconductor liner layer on exposed surfaces of a fin structure that extends above a dielectric isolation structure disposed over a substrate; forming a first capping layer to laterally surround a bottom portion of the semiconductor liner layer; forming a second capping layer over an upper portion of the semiconductor liner layer; and annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing driving a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in a bottom portion of the fin structure is different from a dopant concentration profile in an upper portion of the fin structure.
    Type: Application
    Filed: March 22, 2022
    Publication date: July 7, 2022
    Inventors: Wei-Chih Kao, Hsin-Che Chiang, Yu-San Chien, Chun-Sheng Liang, Kuo-Hua Pan
  • Semiconductor device and method of forming the same
    Patent number: 11374006
    Abstract: Provided are a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a plurality of hybrid fins, a gate, and a dielectric structure. The substrate includes a plurality of fins. The plurality of hybrid fins are respectively disposed between the plurality of fins. The gate covers portions of the plurality of fins and the plurality of hybrid fins. The dielectric structure lands on one of the plurality of hybrid fins to divide the gate into two segment. The two segments are electrically isolated to each other by the dielectric structure and the one of the plurality of hybrid fins.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: June 28, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-San Chien, Chun-Sheng Liang, Jhon-Jhy Liaw, Kuo-Hua Pan, Hsin-Che Chiang
  • Semiconductor device structure and method for forming the same
    Patent number: 11362096
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first device formed over a substrate, and the first device includes a first fin structure. The semiconductor device structure also includes a second device formed over or below the first device, and the second device includes a plurality of second nanostructures stacked in a vertical direction.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ta-Chun Lin, Kuo-Hua Pan
  • METHOD FOR MANUFACTURING EQUAL-STRENGTH STEEL THIN-WALL WELDING COMPONENT WITH ALUMINUM OR ALUMINUM ALLOY PLATING
    Publication number: 20220176490
    Abstract: Disclosed is a method for manufacturing an equal-strength steel thin-wall welding component with an aluminum or aluminum-alloy plating, wherein the plating comprises an intermetallic compound alloy layer in contact with the base body and a metal alloy layer on the intermetallic compound alloy layer; the plating is not removed or thinned before or during welding; and by presetting a welding gap and using a carbon-manganese-steel welding wire, a welding process and protective gas for welding, the tensile strength of a welding seam of the welding component after hot stamping processing is greater than the tensile strength of a base metal, and the elongation of a welded joint is greater than 4% Further disclosed are a welding wire for welding and an equal-strength steel thin-wall welding component with an aluminum or aluminum-alloy plating.
    Type: Application
    Filed: March 6, 2020
    Publication date: June 9, 2022
    Applicant: BAOSHAN IRON & STEEL CO., LTD.
    Inventors: Hua PAN, Chengjie LIU, Ming LEI, Yue WU, Zhongqu SUN, Haomin JIANG
  • DIFFERENT-STRENGTH STEEL WELDING COMPONENT WITH ALUMINUM OR ALUMINUM-ALLOY PLATING AND METHOD FOR MANUFACTURING SAME
    Publication number: 20220168845
    Abstract: Disclosed is a different-strength steel welding component with an aluminum or aluminum-alloy plating formed by means of butt welding of a high-strength steel plate and a low-strength steel plate, and each of the high-strength steel plate and the low-strength steel plate comprises a base body and at least one pure aluminum or aluminum-alloy plating on a surface of the base body. The tensile strength of a welding seam of the welding component after hot stamping is greater than the tensile strength of a low-strength steel base metal, and the elongation is greater than 4%, such that application requirements of the welding component in the field of automobile hot stamping are met. The present disclosure also relates to a method for manufacturing a different-strength steel welding component with an aluminum or aluminum-alloy plating and a welding wire used in the method.
    Type: Application
    Filed: March 27, 2020
    Publication date: June 2, 2022
    Applicant: BAOSHAN IRON & STEEL CO., LTD.
    Inventors: Hua PAN, Chengjie LIU, Ming LEI, Yue WU, Zhongqu SUN, Haomin JIANG
  • Isolation structure for for isolating epitaxially grown source/drain regions and method of fabrication thereof
    Patent number: 11349002
    Abstract: A first source/drain structure is disposed over a substrate. A second source/drain structure is disposed over the substrate. An isolation structure is disposed between the first source/drain structure and the second source/drain structure. The first source/drain structure and a first sidewall of the isolation structure form a first interface that is substantially linear. The second source/drain structure and a second sidewall of the isolation structure form a second interface that is substantially linear. A first source/drain contact surrounds the first source/drain structure in multiple directions. A second source/drain contact surrounds the second source/drain structure in multiple directions. The isolation structure is disposed between the first source/drain contact and the second source/drain contact.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: May 31, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun Lin, Kuan-Lin Yeh, Chun-Jun Lin, Kuo-Hua Pan, Mu-Chi Chiang, Jhon Jhy Liaw
  • Nanoparticle delivery system for diseases associated with major basement membrane components of blood vessels accessible from blood stream
    Patent number: 11337931
    Abstract: A targeting nanoparticle composition and method of treatment for diseases associated with major basement membrane components of blood vessels accessible from blood stream is presented. The composition includes pegylated perfluorocarbon nanoparticles having a targeting ligand attached that targets the basement membrane components, specifically collagen IV. The targeted nanoparticles may contain at least one pharmaceutically active agent capable of treating a glomerular disease such as lupus nephritis.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: May 24, 2022
    Assignee: University of South Florida
    Inventors: Ruisheng Liu, Samuel A. Wickline, Jin Wei, Hua Pan, Jie Zhang
  • SEMICONDUCTOR STRUCTURE WITH EXTENDED CONTACT STRUCTURE
    Publication number: 20220157938
    Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. The semiconductor structure further includes a gate structure surrounding the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure further includes a contact formed over the source/drain structure and extending into the source/drain structure.
    Type: Application
    Filed: February 7, 2022
    Publication date: May 19, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun LIN, Kuo-Hua PAN, Jhon-Jhy LIAW, Chao-Ching CHENG, Hung-Li CHIANG, Shih-Syuan HUANG, Tzu-Chiang CHEN, I-Sheng CHEN, Sai-Hooi YEONG
  • ISOLATION WITH MULTI-STEP STRUCTURE
    Publication number: 20220149039
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and an adjacent second fin structure protruding from the semiconductor substrate and an isolation structure formed in the semiconductor substrate and in direct contact with the first fin structure and the second fin structure. The first fin structure and the second fin structure each include a first portion protruding above a top surface of the isolation structure, a second portion in direct contact with a bottom surface of the first portion, and a third portion extending from a bottom of the second portion. A top width of the third portion is different than a bottom width of the third portion and a bottom width of the second portion.
    Type: Application
    Filed: January 25, 2022
    Publication date: May 12, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun LIN, Tien-Shao CHUANG, Kuang-Cheng TAI, Chun-Hung CHEN, Chih-Hung HSIEH, Kuo-Hua PAN, Jhon-Jhy LIAW
  • Epitaxial blocking layer for multi-gate devices and fabrication methods thereof
    Patent number: 11315785
    Abstract: A method includes providing a semiconductor substrate; epitaxially growing a blocking layer from a top surface of the semiconductor substrate, wherein the blocking layer has a lattice constant different from the semiconductor substrate; epitaxially growing a semiconductor layer above the blocking layer; patterning the semiconductor layer to form a semiconductor fin, wherein the blocking layer is under the semiconductor fin; forming a source/drain (S/D) feature in contact with the semiconductor fin; and forming a gate structure engaging the semiconductor fin.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: April 26, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Che Chiang, Wei-Chih Kao, Chun-Sheng Liang, Kuo-Hua Pan
  • Isolation structure for preventing unintentional merging of epitaxially grown source/drain
    Patent number: 11315924
    Abstract: A semiconductor device includes a first active region and a second active region disposed over a substrate. A first source/drain component is grown on the first active region. A second source/drain component is grown on the second active region. An interlayer dielectric (ILD) is disposed around the first source/drain component and the second source/drain component. An isolation structure extends vertically through the ILD. The isolation structure separates the first source/drain component from the second source/drain component.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: April 26, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ta-Chun Lin, Kuan-Lin Yeh, Chun-Jun Lin, Kuo-Hua Pan, Mu-Chi Chiang
  • Semiconductor devices having gate dielectric layers of varying thicknesses and methods of forming the same
    Patent number: 11302692
    Abstract: A semiconductor device includes a substrate; an I/O device over the substrate; and a core device over the substrate. The I/O device includes a first gate structure having an interfacial layer; a first high-k dielectric stack over the interfacial layer; and a conductive layer over and in physical contact with the first high-k dielectric stack. The core device includes a second gate structure having the interfacial layer; a second high-k dielectric stack over the interfacial layer; and the conductive layer over and in physical contact with the second high-k dielectric stack. The first high-k dielectric stack includes the second high-k dielectric stack and a third dielectric layer.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: April 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ta-Chun Lin, Kuo-Hua Pan, Jhon Jhy Liaw, Shien-Yang Wu
  • Isolation Structure for for Isolating Epitaxially Grown Source/Drain Regions and Method of Fabrication Thereof
    Publication number: 20220102509
    Abstract: A first source/drain structure is disposed over a substrate. A second source/drain structure is disposed over the substrate. An isolation structure is disposed between the first source/drain structure and the second source/drain structure. The first source/drain structure and a first sidewall of the isolation structure form a first interface that is substantially linear. The second source/drain structure and a second sidewall of the isolation structure form a second interface that is substantially linear. A first source/drain contact surrounds the first source/drain structure in multiple directions. A second source/drain contact surrounds the second source/drain structure in multiple directions. The isolation structure is disposed between the first source/drain contact and the second source/drain contact.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 31, 2022
    Inventors: Ta-Chun Lin, Kuan-Lin Yeh, Chun-Jun Lin, Kuo-Hua Pan, Mu-Chi Chiang, Jhon Jhy Liaw
  • IDENTIFICATION OF MUTATIONS IN CHANNELOPSIN VARIANTS HAVING IMPROVED LIGHT SENSITIVITY AND METHODS OF USE THEREOF
    Publication number: 20220089660
    Abstract: The invention provides compositions and kits including at least one nucleic acid or polypeptide molecule encoding for a mutant CoChop protein. Methods of the invention include administering a composition comprising a mutant CoChop to a subject to preserve, improve, or restore phototransduction. Preferably, the compositions and methods of the invention are provided to a subject having impaired vision, thereby restoring vision to normal levels.
    Type: Application
    Filed: May 19, 2021
    Publication date: March 24, 2022
    Inventor: Zhuo-Hua Pan