Abstract: The present disclosure provides compounds of Formulas (I), (II), and pharmaceutically acceptable salts thereof. The compounds described herein are useful in treating proliferative diseases, for example, cancer (e.g., lung cancer), and infectious diseases (e.g., bacterial infections).

Abstract: A method includes depositing a semiconductor stack within a first region and a second region on a substrate, the semiconductor stack having alternating layers of a first type of semiconductor material and a second type of semiconductor material. The method further includes removing a portion of the semiconductor stack from the second region to form a trench and with an epitaxial growth process, filling the trench with the second type of semiconductor material. The method further includes patterning the semiconductor stack within the first region to form a nanostructure stack, patterning the second type of semiconductor material within the second region to form a fin structure, and forming a gate structure over both the nanostructure stack and the fin structure.

Abstract: A semiconductor structure includes a semiconductor fin protruding from a substrate, an S/D feature disposed over the semiconductor fin, and a first dielectric fin and a second dielectric fin disposed over the substrate, where the semiconductor fin is disposed between the first dielectric fin and the second dielectric fin, where a first air gap is enclosed by a first sidewall of the epitaxial S/D feature and the first dielectric fin, and where a second air gap is enclosed by a second sidewall of the epitaxial S/D feature and the second dielectric fin.

Abstract: The present disclosure relates to nanoparticles and methods for polynucleotide transfection.

Abstract: A first electrical connector, a second electrical connector and an electrical connector assembly are provided.

Abstract: Semiconductor structures and methods are provided. A semiconductor structure according to an embodiment includes a first cell disposed over a first well doped with a first-type dopant, a second cell disposed over the first well, and a tap cell disposed over a second well doped with a second-type dopant different from the first-type dopant. The tap cell is sandwiched between the first cell and the second cell. The first cell includes a first plurality of transistors and the second cell includes a second plurality of transistors.

Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. The via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. The first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. The via bulk layer can include tungsten and/or cobalt. A capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. In some implementations, the capping layer includes cobalt and silicon.

Abstract: An energy conversion device is provided. The device includes: a reversible pulse width modulation (PWM) rectifier (11) and a motor coil (12), where the motor coil (12) includes at least a first winding unit and a second winding unit, and the first winding unit and the second winding unit are both connected with the reversible PWM rectifier (11). The first winding unit is connected with at least one of neutral lines in the second winding unit, where at least one neutral line of at least one of the winding units is connected with a first end of a first direct current (DC) charging and discharging port (3), the reversible PWM rectifier (11) is connected with a first end of a external battery (2) and a second end of the external battery (2) respectively, and a second end of the first DC charging and discharging port (3) is connected with the second end of the external battery (2).

Abstract: The present invention discloses an ultra-quiet backing-paper-free cold laminating film comprising a substrate layer, a release layer, and an adhesive layer, the release layer and the adhesive layer being each attached to a respective side of the substrate layer, the release layer being obtained by drying a release agent applied on the substrate layer, and the release agent consisting of the following components by weight: 2-ethylhexyl acrylate, vinyltrimethoxysilane, 1-methyl-1-phenylethyl hydroperoxide, vinyl-terminated silicone resin, di-t-butyl cumene peroxide, fluorosiloxane, ethyl acetate, ethylene glycol dimethyl ether, a toughening agent, polysiloxane-polyether copolymer, silicone and wax powder.

Abstract: A semiconductor structure includes a first semiconductor device formed over a substrate and a second semiconductor device formed over the substrate. The first semiconductor device includes a first source/drain feature over the substrate, a first gate structure over the substrate, a first conductive feature over the first source/drain feature, and a first insulation layer between the first gate structure and the first conductive feature. The second semiconductor device includes a second source/drain feature over the substrate, a second gate structure over the substrate, a second conductive feature over the second source/drain feature, and a second insulation layer between the second gate structure and the second conductive feature. A width of the first conductive feature and a width of the second conductive feature are different, and a width of the first insulation layer is less than a width of the second insulation layer.

Abstract: A cooperative control method for an energy conversion apparatus is disclosed.

Abstract: The present disclosure provides a fabrication method that includes providing a workpiece having a semiconductor substrate that includes a first circuit area and a second circuit area; forming a first active region in the first circuit area and a second active region on the second circuit area; forming first stacks with a first gate spacing on the first active region and second gate stacks with a second gate spacing on the second active region, the second gate spacing being different from the first gate spacing; performing an ion implantation to introduce a doping species to the first active region; performing an etching process, thereby recessing both first source/drain regions of the first active region with a first etch rate and second source/drain regions of the second active region; and epitaxially growing first source/drain features within the first source/drain regions and second source/drain features within the second source/drain regions.

Abstract: A dummy fin described herein includes a low dielectric constant (low-k or LK) material outer shell. A leakage path that would otherwise occur due to a void being formed in the low-k material outer shell is filled with a high dielectric constant (high-k or HK) material inner core. This increases the effectiveness of the dummy fin to provide electrical isolation and increases device performance of a semiconductor device in which the dummy fin is included. Moreover, the dummy fin described herein may not suffer from bending issues experienced in other types of dummy fins, which may otherwise cause high-k induced alternating current (AC) performance degradation. The processes for forming the dummy fins described herein are compatible with other fin field effect transistor (finFET) formation processes and are be easily integrated to minimize and/or prevent polishing issues, etch back issues, and/or other types of semiconductor processing issues.

Abstract: Transistors of different types of electronic devices on the same semiconductor substrate are configured with different transistor attributes to increase the performance of the different types of electronic devices. Fin height, shallow source drain (SSD) height, source or drain width, and/or one or more other transistor attributes may be co-optimized for the different types of electronic devices by various semiconductor manufacturing processes such as etching, lithography, process loading, and/or masking, among other examples. This enables the performance of a plurality of types of electronic devices on the same semiconductor substrate to be increased.

Abstract: A method of forming a semiconductor structure includes forming a semiconductor fin over a substrate, forming a dummy gate stack over the semiconductor fin, depositing a dielectric layer over the dummy gate stack, and selectively etching the dielectric layer, such that a top portion and a bottom portion of the dielectric layer form a step profile. The method further includes removing portions of the dielectric layer to form a gate spacer and subsequently forming a source/drain feature in the semiconductor fin adjacent to the gate spacer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first device formed over a substrate, wherein the first device includes a first fin structure and a first S/D structure formed over the first fin structure. The semiconductor device structure includes a second device formed over or below the first device, and the second device includes a plurality of second nanostructures stacked in a vertical direction. The semiconductor device structure also includes a second S/D structure formed over the second nanostructures, and the second S/D structure is directly above or below the first S/D structure.

Abstract: A first source/drain structure is disposed over a substrate. A second source/drain structure is disposed over the substrate. An isolation structure is disposed between the first source/drain structure and the second source/drain structure. The first source/drain structure and a first sidewall of the isolation structure form a first interface that is substantially linear. The second source/drain structure and a second sidewall of the isolation structure form a second interface that is substantially linear. A first source/drain contact surrounds the first source/drain structure in multiple directions. A second source/drain contact surrounds the second source/drain structure in multiple directions. The isolation structure is disposed between the first source/drain contact and the second source/drain contact.

Abstract: The present invention relates to the technical field of vehicles, and provides an energy conversion device and a vehicle. The energy conversion device includes a reversible pulse-width modulation (PWM) rectifier, a motor coil connected with the reversible PWM rectifier, a one-way conduction module, and a capacitor. A DC charging circuit or a DC discharging circuit is formed by an external DC port with an external battery by using the energy conversion device, and a driving circuit is formed by the external battery with the reversible PWM rectifier and the motor coil in the energy conversion device. The one-way conduction module is connected between a first end of the capacitor and a second end of the external DC port, or the one-way conduction module is connected between a second end of the capacitor and a first end of the external DC port.

Abstract: The present disclosure provides compounds of Formulas (I), (II), and pharmaceutically acceptable salts thereof. The compounds described herein are useful in treating proliferative diseases, for example, cancer (e.g., lung cancer), and infectious diseases (e.g., bacterial infections).

Abstract: Provided is a semiconductor device including a substrate, one hybrid fin, a gate, and a dielectric structure. The substrate includes at least two fins. The hybrid fin is disposed between the at least two fins. The gate covers portions of the at least two fins and the hybrid fin. The dielectric structure lands on the hybrid fin to divide the gate into two segment. The two segments are electrically isolated to each other by the dielectric structure and the hybrid fin. The hybrid fin includes a first portion, disposed between the two segments of the gate; and a second portion, disposed aside the first portion, wherein a top surface of the second portion is lower than a top surface of the first portion.