Patents by Inventor Hua Pan

Hua Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230344375
    Abstract: A control method for an electric drive system of a vehicle, includes: acquiring a shaft torque of the electric motor and a present operating point of the vehicle in response to a vehicle heating demand signal; acquiring a present heat generation power of the electric drive system accordingly; determining a current adjustment amplitude accordingly; acquiring a three-phase current value and a position value of the electric motor, and a present direct axis current value and a present quadrature axis current value of the electric motor at the present operating point accordingly; controlling the present direct axis current value to oscillate at a change frequency and the current adjustment amplitude to obtain a target direct axis current value; acquiring a target quadrature axis current value accordingly; acquiring an electric motor drive signal accordingly.
    Type: Application
    Filed: June 28, 2023
    Publication date: October 26, 2023
    Inventors: Heping LING, Hua PAN, Yuxin ZHANG, Guowei QIU, Chen HONG
  • Patent number: 11799017
    Abstract: An embodiment method includes: forming a semiconductor liner layer on exposed surfaces of a fin structure that extends above a dielectric isolation structure disposed over a substrate; forming a first capping layer to laterally surround a bottom portion of the semiconductor liner layer; forming a second capping layer over an upper portion of the semiconductor liner layer; and annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing driving a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in a bottom portion of the fin structure is different from a dopant concentration profile in an upper portion of the fin structure.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: October 24, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Wei-Chih Kao, Hsin-Che Chiang, Yu-San Chien, Chun-Sheng Liang, Kuo-Hua Pan
  • Publication number: 20230335643
    Abstract: A semiconductor device includes a substrate, an epitaxial structure over the substrate, a conductive structure, and a dielectric liner. The conductive structure extends from within the epitaxial structure to above the epitaxial structure. The dielectric liner extends along a sidewall of the conductive structure. The dielectric liner has a top end capped by the conductive structure.
    Type: Application
    Filed: June 21, 2023
    Publication date: October 19, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Che TSAI, Min-Yann HSIEH, Hua-Feng CHEN, Kuo-Hua PAN
  • Publication number: 20230335619
    Abstract: A semiconductor structure includes a first active region over a substrate and extending along a first direction, a gate structure over the first active region and extending along a second direction substantially perpendicular to the first direction, a gate-cut feature abutting an end of the gate structure, and a channel isolation feature extending along the second direction and between the first active region and a second active region. The gate structure includes a metal electrode in direct contact with the gate-cut feature. The channel isolation feature includes a liner on sidewalls extending along the second direction and a dielectric fill layer between the sidewalls. The gate-cut feature abuts an end of the channel isolation feature and the dielectric fill layer is in direct contact with the gate-cut feature.
    Type: Application
    Filed: June 26, 2023
    Publication date: October 19, 2023
    Inventors: Ta-Chun Lin, Jhon Jhy Liaw, Kuo-Hua Pan
  • Patent number: 11791217
    Abstract: A structure includes a fin on a substrate; first and second gate stacks over the fin and including first and second gate dielectric layers and first and second gate electrodes respectively; and a dielectric gate over the fin and between the first and second gate stacks. The dielectric gate includes a dielectric material layer on a third gate dielectric layer. In a cross-sectional view cut along a direction parallel to a lengthwise direction of the fin and offset from the fin, the first gate dielectric layer forms a first U shape, the third gate dielectric layer forms a second U shape, a portion of the first gate electrode is disposed within the first U shape, a portion of the dielectric material layer is disposed within the second U shape, and a portion of an interlayer dielectric layer is disposed laterally between the first and the second U shapes.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: October 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ta-Chun Lin, Buo-Chin Hsu, Kuo-Hua Pan, Jhon Jhy Liaw, Chih-Yung Lin
  • Publication number: 20230326999
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack over a substrate. The method includes forming a spacer structure over a sidewall of the gate stack. The method includes forming a source/drain structure in and over the substrate, wherein a portion of the spacer structure is between the source/drain structure and the gate stack. The method includes partially removing the outer layer, wherein a first lower portion of the outer layer remains between the source/drain structure and the gate stack. The method includes partially removing the middle layer, wherein a second lower portion of the middle layer remains between the source/drain structure and the gate stack.
    Type: Application
    Filed: April 11, 2022
    Publication date: October 12, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ta-Chun LIN, Ming-Che CHEN, Chun-Jun LIN, Kuo-Hua PAN, Jhon-Jhy LIAW
  • Patent number: 11779544
    Abstract: The present disclosure is directed to antithrombotic nanoparticles and methods of treating necrotizing enterocolitis.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: October 10, 2023
    Assignee: University of South Florida
    Inventors: Akhil Maheshwari, Samuel Wickline, Kopperuncholan Namachivayam, Hua Pan
  • Publication number: 20230310657
    Abstract: The invention provides nucleic acids and nucleic acid expression vectors containing optimized mGluR6 promoters for expression of transgenes in the retina. The compositions and methods of the invention are useful for expression of gene products to preserve, improve, or restore phototransduction or vision.
    Type: Application
    Filed: January 11, 2023
    Publication date: October 5, 2023
    Applicant: Wayne State University
    Inventors: Zhuo-Hua Pan, Qi Lu, Tushar H. Ganjawala, JrGang Cheng
  • Publication number: 20230320058
    Abstract: Methods and structures for the co-optimization of memory and logic devices. A device includes a substrate having a first region and a second region. The device may include a first gate structure disposed in the first region and a second gate structure disposed in the second region. The device may further include a first source/drain feature disposed adjacent to the first gate structure and a second source/drain feature disposed adjacent to the second gate structure. A first top surface of the first source/drain feature and a second top surface of the second source/drain feature are substantially level. A first bottom surface of the first source/drain feature is a first distance away from the first top surface, and a second bottom surface of the second source/drain feature is a second distance away from the second top surface. In some cases, the second distance is greater than the first distance.
    Type: Application
    Filed: July 21, 2022
    Publication date: October 5, 2023
    Inventors: Ta-Chun Lin, Chih-Hung Hsieh, Chun-Jun Lin, Kuo-Hua Pan, Jhon Jhy Liaw
  • Publication number: 20230307299
    Abstract: The present disclosure provides a fabrication method that includes providing a workpiece having a semiconductor substrate with a first circuit area and a second circuit area; forming a first active region within the first circuit area and a second active region within the second circuit area; forming a first gate structure on the first active region and a second gate structure on the second active region; introducing a doping species to the first active region but not the second active region; performing an etching process, thereby simultaneously recessing both first source/drain regions of the first active region and second source/drain regions of the second active region at a same etch rate; and thereafter, epitaxially growing first source/drain features within the first source/drain regions and second source/drain features within the second source/drain regions.
    Type: Application
    Filed: May 22, 2023
    Publication date: September 28, 2023
    Inventors: Ta-Chun Lin, Kuo-Hua Pan, Jhon Jhy Liaw
  • Patent number: 11756962
    Abstract: Provided is a semiconductor device including a substrate, one hybrid fin, a gate, and a dielectric structure. The substrate includes at least two fins. The hybrid fin is disposed between the at least two fins. The gate covers portions of the at least two fins and the hybrid fin. The dielectric structure lands on the hybrid fin to divide the gate into two segment. The two segments are electrically isolated to each other by the dielectric structure and the hybrid fin. The hybrid fin includes a first portion, disposed between the two segments of the gate; and a second portion, disposed aside the first portion, wherein a top surface of the second portion is lower than a top surface of the first portion.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: September 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-San Chien, Chun-Sheng Liang, Jhon-Jhy Liaw, Kuo-Hua Pan, Hsin-Che Chiang
  • Patent number: 11749683
    Abstract: A semiconductor device includes a first active region and a second active region disposed over a substrate. A first source/drain component is grown on the first active region. A second source/drain component is grown on the second active region. An interlayer dielectric (ILD) is disposed around the first source/drain component and the second source/drain component. An isolation structure extends vertically through the ILD. The isolation structure separates the first source/drain component from the second source/drain component.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: September 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.
    Inventors: Ta-Chun Lin, Kuan-Lin Yeh, Chun-Jun Lin, Kuo-Hua Pan, Mu-Chi Chiang
  • Patent number: 11749677
    Abstract: A semiconductor structure includes a first semiconductor device formed over a substrate and a second semiconductor device formed over the substrate. The first semiconductor device includes a first source/drain feature over the substrate, a first gate structure over the substrate, a first conductive feature over the first source/drain feature, and a first insulation layer between the first gate structure and the first conductive feature. The second semiconductor device includes a second source/drain feature over the substrate, a second gate structure over the substrate, a second conductive feature over the second source/drain feature, and a second insulation layer between the second gate structure and the second conductive feature. A width of the first conductive feature and a width of the second conductive feature are different, and a width of the first insulation layer is less than a width of the second insulation layer.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: September 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun Lin, Kuo-Hua Pan, Jhon Jhy Liaw
  • Publication number: 20230274562
    Abstract: Bootstrapped semantic preprocessing techniques for medical datasets such as whole slide histopathology image datasets can be used to more efficiently and effectively train artificial intelligence used for medical purposes. The bootstrapped semantic preprocessing techniques generally include deriving metrics from image features and adjusting images according to the metrics. This process can be repeated iteratively for unknown and unlabeled data using a bootstrapping technique to normalize unknown samples to the training dataset distribution.
    Type: Application
    Filed: February 27, 2023
    Publication date: August 31, 2023
    Inventors: Christopher Collazo, Lawrence Hall, Dmitry Goldgof, Samuel Wickline, Hua Pan
  • Patent number: 11742349
    Abstract: A method includes forming a first channel region, a second channel region, and a third channel region over a substrate, depositing a first interfacial layer over the first, second, and third channel regions, removing the first interfacial layer from the first and second channel regions, depositing a second interfacial layer over the first and second channel regions, thinning a thickness of the second interfacial layer over the first channel region, depositing a high-k dielectric layer over the first, second, and third channel regions, and forming a gate electrode layer over the first, second, and third channel regions.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Ta-Chun Lin, Kuo-Hua Pan, Jhon Jhy Liaw, Shien-Yang Wu
  • Publication number: 20230263855
    Abstract: The present disclosure relates to nanoparticles and methods for polynucleotide transfection.
    Type: Application
    Filed: November 18, 2022
    Publication date: August 24, 2023
    Inventors: Samuel A. Wickline, Hua Pan, Christine Thien-Nga Pham, Huimin Yan
  • Publication number: 20230260796
    Abstract: In a method of manufacturing a semiconductor device, an initial pattern layout is obtained. The initial pattern layout incudes fin patterns which include active fin patterns to be formed as active fin structures and dummy fin patterns not to be formed as actual fin structures or to be removed. The locations of the fin patterns are modified, as follows. A space between adjacent active fin patterns is increased by a first amount, a space between the dummy fin patterns is decreased by a second amount, and a space between one of the dummy fin patterns and one of the active fin patterns adjacent to the one of the dummy fin patterns is decreased by a third amount. Mandrel patterns are placed so that the fin patterns of which locations are modified are placed along longitudinal edges of the mandrel patterns.
    Type: Application
    Filed: May 24, 2022
    Publication date: August 17, 2023
    Inventors: Yu-Jen CHANG, Chih-Yang CHEN, Hua Feng CHEN, Kuo-Hua PAN, Mu-Chi CHIANG
  • Patent number: 11728206
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and an adjacent second fin structure protruding from the semiconductor substrate and an isolation structure formed in the semiconductor substrate and in direct contact with the first fin structure and the second fin structure. The first fin structure and the second fin structure each include a first portion protruding above a top surface of the isolation structure, a second portion in direct contact with a bottom surface of the first portion, and a third portion extending from a bottom of the second portion. A top width of the third portion is different than a bottom width of the third portion and a bottom width of the second portion.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun Lin, Tien-Shao Chuang, Kuang-Cheng Tai, Chun-Hung Chen, Chih-Hung Hsieh, Kuo-Hua Pan, Jhon-Jhy Liaw
  • Patent number: 11721763
    Abstract: A method comprises forming a source/drain region on a substrate; forming a dielectric layer over the source/drain region; forming a contact hole in the dielectric layer; forming a contact hole liner in the contact hole; removing a first portion of the contact hole liner to expose a sidewall of the contact hole; etching the exposed sidewall of the contact hole to laterally expand the contact hole; and forming a contact plug in the laterally expanded contact hole.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: August 8, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Che Tsai, Min-Yann Hsieh, Hua-Feng Chen, Kuo-Hua Pan
  • Publication number: 20230238603
    Abstract: The present disclosure relates to a battery energy processing device and method and a vehicle. The battery energy processing device includes: a bridge arm converter, having a first bus terminal connected with a positive electrode of a battery and a second bus terminal connected with a negative electrode of the battery; a motor winding, having a first end connected with a midpoint of the bridge arm converter; an energy storage device, respectively connected with a second end of the motor winding and the second bus terminal; and a controller, configured to control, in a first preset state, the bridge arm converter to charge and discharge the battery, so as to realize heating of the battery. In this way, the charging and discharging of the battery can be controlled, and internal resistance of the battery causes the battery to generate a large amount of heat, which causes a temperature rise of the battery, thereby realizing the heating of the battery.
    Type: Application
    Filed: June 4, 2021
    Publication date: July 27, 2023
    Inventors: Yubo LIAN, Heping LING, Hua PAN, Lei YAN, Feiyue XIE