Abstract: A semiconductor device structure includes a first dielectric wall, a plurality of first semiconductor layers vertically stacked and extending outwardly from a first side of the first dielectric wall, each first semiconductor layer has a first width, a plurality of second semiconductor layers vertically stacked and extending outwardly from a second side of the first dielectric wall, each second semiconductor layer has a second width, a plurality of third semiconductor layers disposed adjacent the second side of the first dielectric wall, each third semiconductor layer has a third width greater than the second width, a first gate electrode layer surrounding at least three surfaces of each of the first semiconductor layers, the first gate electrode layer having a first conductivity type, and a second gate electrode layer surrounding at least three surfaces of each of the second semiconductor layers, the second gate electrode layer having a second conductivity type opposite the first conductivity type.

Abstract: Various embodiments of the teachings herein include an image processing system comprising: a video stream processing device configured to receive a video stream, segment the video stream into multiple frames of pictures arranged in chronological order, and distribute the multiple frames of pictures to edge computing devices in a connected edge computing device group; and a picture collecting device configured to receive pictures from the edge computing device group. The individual edge computing devices in the edge computing device group are each configured to subject the received pictures to target identification, and send the pictures marked with a region in which an identified target is located. The picture collecting device is further configured to restore in chronological order as a video stream the received pictures marked with target identification results.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a first stack structure formed over a substrate, and the first stack structure includes a plurality of nanostructures that extend along a first direction. The semiconductor structure includes a second stack structure formed adjacent to the first stack structure, and the second stack structure includes a plurality of nanostructures that extend along the first direction. The semiconductor structure includes a first gate structure formed over the first stack structure, and the first gate structure extends along a second direction. The semiconductor structure also includes a dielectric wall between the first stack structure and the second stack structure, and the dielectric wall includes a low-k dielectric material, and the dielectric wall is connected to the first stack structure and the second stack structure.

Abstract: A semiconductor device includes a semiconductor substrate having a first lattice constant, a dopant blocking layer disposed over the semiconductor substrate, the dopant blocking layer having a second lattice constant different from the first lattice constant, and a buffer layer disposed over the dopant blocking layer, the buffer layer having a third lattice constant different from the second lattice constant. The semiconductor device also includes a plurality of channel members suspended over the buffer layer, an epitaxial feature abutting the channel members, and a gate structure wrapping each of the channel members.

Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. The semiconductor structure further includes a gate structure surrounding the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure further includes a contact formed over the source/drain structure and extending into the source/drain structure.

Abstract: A semiconductor device and method of forming the same are disclosed. The semiconductor device includes a fin structure, a gate electrode, a source-drain region, a plug and a hard mask structure. The gate electrode crosses over the fin structure. The source-drain region in the fin structure is aside the gate electrode. The plug is disposed over and electrically connected to the gate electrode. The hard mask structure surrounds the plug and is disposed over the gate electrode, wherein the hard mask structure includes a first hard mask layer and a second hard mask layer, the second hard mask layer covers a sidewall and a top surface of the first hard mask layer, and a material of the first hard mask layer is different from a material of the second hard mask layer.

Abstract: The present disclosure provides compounds of Formulas (I), (II), and pharmaceutically acceptable salts thereof. The compounds described herein are useful in treating proliferative diseases, for example, cancer (e.g., lung cancer), and infectious diseases (e.g., bacterial infections).

Abstract: A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.

Abstract: A motor control circuit includes a first switch module, a three-phase inverter, and a control module. A power supply module, the first switch module, the three-phase inverter, and a three-phase alternating current motor form a current loop; midpoints of three phase legs of the three-phase inverter are respectively connected to three phase coils of the three-phase alternating current motor; the three-phase alternating current motor is configured to input or output a current by using a wire N extending from a connection point of the three phase coils; the control module is connected to the three-phase inverter, first switch module, three-phase alternating current motor, and power supply module; the control module is configured to control the three-phase inverter to enable the motor control circuit to receive a voltage of the power supply module and output a direct current, and to boost a voltage of the power supply module.

Abstract: Embodiments provide a method for forming a semiconductor device structure, includes forming a fin structure having first semiconductor layers and second semiconductor layers alternatingly stacked thereover, forming a sacrificial gate structure over a portion of the fin structure, removing portions of the sacrificial gate structure to expose the first and second semiconductor layers, removing portions of the second semiconductor layers to expose portions of each of the first semiconductor layers. The method includes surrounding the exposed portions of each of the first semiconductor layers with a cladding layer, wherein the cladding layer is formed of a material chemically different from the first semiconductor layers, and the cladding layer has a first atomic percentage of germanium.

Abstract: A method of forming a semiconductor device structure is provided. The method includes forming a plurality of dummy gates over a substrate and performing a first etch step and a second etch step on the substrate exposed between the dummy gates. The first etch step includes an anisotropic etching process and an isotropic etching process. The second includes an isotropic etching step.

Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. The via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. The first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. The via bulk layer can include tungsten and/or cobalt. A capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. In some implementations, the capping layer includes cobalt and silicon.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a gate structure formed over a substrate, and a first source/drain (S/D) structure formed adjacent to the gate structure. The semiconductor structure includes an S/D contact structure formed over the first S/D structure, and a dielectric wall formed below the gate structure and the S/D contact structure. The dielectric wall has a first portion directly below the S/D contact structure and a second portion directly below the gate structure, the first portion has a first height along a vertical direction, the second portion has a second height along the vertical direction, and the first height is smaller than the second height.

Abstract: A method for controlling an electric drive system, includes: determining that the vehicle is in a traveling condition; obtaining a rotation speed value, a shaft end torque value, a present direct axis current value, and a present quadrature axis current value of the motor when receiving a vehicle heat-up demand signal; determining a target torque curve according to the shaft end torque value, and determining a target traveling heating calibration curve according to the vehicle heat-up demand signal and the rotation speed value; determining an intersection of the target torque curve and the target traveling heating calibration curve as a target traveling condition point; determining a target quadrature axis current value and a target direct axis current value according to the target traveling condition point; and controlling, according to the target direct axis current value and the target quadrature axis current value, the motor to operate.

Abstract: A method includes forming a semiconductor fin over a substrate; forming isolation structures laterally surrounding the semiconductor fin; forming a gate structure over the semiconductor fin; forming a first spacer layer and a second spacer layer over the gate structure and the semiconductor fin; etching back the second spacer layer, such that a top surface of the second spacer layer is lower than a top surface of the first spacer layer; after etching back the second spacer layer, forming a third spacer layer over the first spacer layer and the second spacer layer; etching the first, second, and third spacer layers and the semiconductor fin to form recesses; and forming epitaxial source/drain structures in the recesses.

Abstract: Nucleic acid vectors encoding light-gated cation-selective membrane channels, in particular channelrhodopsin-2 (Chop2), converted inner retinal neurons to photosensitive cells in photoreceptor-degenerated retina in an animal model. Such treatment restored visual perception and various aspects of vision. A method of restoring light sensitivity to a retina of a subject suffering from vision loss due to photoreceptor degeneration, as in retinitis pigmentosa or macular degeneration, is provided. The method comprises delivering to the subject by intravitreal or subretinal injection, the above nucleic acid vector which comprises an open reading frame encoding a rhodopsin, to which is operatively linked a promoter and transcriptional regulatory sequences, so that the nucleic acid is expressed in inner retinal neurons.

Abstract: A transmission board includes: an insulating carrier; a pair of differential channels, including a first channel and a second channel; and a grounding structure, provided in the insulating carrier. An inner side of the first channel and an inner side of the second channel are separated from and coupled to each other. The first channel has a timing compensation section and a connecting section connected to the timing compensation section. A distance between an inner side of the timing compensation section and the inner side of the second channel is defined as a first distance. A distance between an inner side of the connecting section and the inner side of the second channel is defined as a second distance. The first distance is greater than the second distance. The grounding structure is located between the inner side of the timing compensation section and the inner side of the second channel.

Abstract: Structures and methods for the co-optimization of various device types include performing a first photolithography and etch process to simultaneously form a first source/drain recess for a first device in a first substrate region and a third source/drain recess for a third device in a third substrate region different than the first substrate region. In some embodiments, the method further includes performing a second photolithography and etch process to form a second source/drain recess for a second device in a second substrate region different than the first and third substrate regions. The method further includes forming a first source/drain feature within the first source/drain recess, a second source/drain feature within the second source/drain recess, and a third source/drain feature within the third source/drain recess.

Abstract: Transistors of different types of electronic devices on the same semiconductor substrate are configured with different transistor attributes to increase the performance of the different types of electronic devices. Fin height, shallow source drain (SSD) height, source or drain width, and/or one or more other transistor attributes may be co-optimized for the different types of electronic devices by various semiconductor manufacturing processes such as etching, lithography, process loading, and/or masking, among other examples. This enables the performance of a plurality of types of electronic devices on the same semiconductor substrate to be increased.

Abstract: In a power battery heating method for a vehicle, when a current temperature value of a power battery is lower than a preset temperature value, and a heating condition of the power battery meets a preset condition, a three-phase inverter is controlled to cause a three-phase alternating current motor to generate heat according to heating energy, to heat a coolant flowing through the power battery, a preset quadrature-axis current that causes a torque value outputted by the motor to be an appropriate value is obtained, and a corresponding preset direct-axis current is obtained according to heating power of the power battery, so as to control, according to the preset direct-axis current and the preset quadrature-axis current, the three-phase inverter to adjust a phase current of the three-phase alternating current motor in the heating process, where a direction of the preset direct-axis current changes periodically in the heating process.