Abstract: A spectral method is provided for partitioning type and loading with aerosol optical depth. Based on multi-spectral optical aerosol depth, particle-size distribution and refractive index are derived by normalizing first- and second-order derivatives for processing quantitative calibration of main components. According to the optical feature parameters of various aerosol types, a radiation theory is applied to simulate multi-spectral optical depth for each density, including those of mixed types. The intrinsic parameters of aerosol types are figured out by constructing normalized derivative aerosol indices (NDAI). The clear characteristic differences between aerosol types are used to figure out main components of aerosols and their mixing ratios. The simulation result of the normalized index of various aerosol type is in good agreement with the ground observation data of Aerosol Robotic Network. It shows that NDAI is quite practicable in quantitative calibration of main components of atmospheric aerosol.

Abstract: A heat dissipation device includes a base having a first surface in contact with at least one heat source and an opposite second surface having a heat dissipation zone upward extended therefrom; an auxiliary heat dissipation zone horizontally extended from one of four lateral sides or directions of the heat dissipation zone; an air guiding section defined at the auxiliary heat dissipation zone; and at least one upward indented zone formed between the auxiliary heat dissipation zone and the side of the heat dissipation zone having the auxiliary heat dissipation zone sideward sidewardly extended from a higher portion thereof. With these arrangements, the heat dissipation device can guide air flow currents directly or indirectly to a plurality of heat sources located corresponding to the heat dissipation zone and the auxiliary heat dissipation zone at the same time to cool them.

Abstract: The present disclosure describes a method and an apparatus that can enhance the slurry oxidizability for a chemical mechanical polishing (CMP) process. The method can include securing a substrate onto a carrier of a polishing system. The method can further include dispensing, via a feeder of the polishing system, a first slurry towards a polishing pad of the polishing system. The method can further include forming a second slurry by enhancing an oxidizability of the first slurry, and performing a polishing process, with the second slurry, on the substrate.

Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming a source/drain region on a side of the dummy gate stack, removing the dummy gate stack to form a trench, depositing a gate dielectric layer extending into the trench, depositing a metal-containing layer over the gate dielectric layer, and depositing a silicon-containing layer on the metal-containing layer. The metal-containing layer and the silicon-containing layer in combination act as a work-function layer. A planarization process is performed to remove excess portions of the silicon-containing layer, the metal-containing layer, and the gate dielectric layer, with remaining portions of the silicon-containing layer, the silicon-containing layer, and the gate dielectric layer forming a gate stack.

Abstract: A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.

Abstract: A temperature measurement system for determining a performance of a smoke generating device includes a temperature measuring device. The temperature measuring device includes an elongated carrier and a number of thermal sensors disposed within the elongated carrier. The elongated carrier is configured to be inserted into an elongated chamber of the smoke generating device. Each of the thermal sensors includes a sensing end exposed on an outer surface of the elongated carrier. When the elongated carrier is inserted into the elongated chamber, the sensing ends respectively detect a temperature of a number of heating members of the smoke generating device.

Abstract: A spectral method is provided for partitioning type and loading with aerosol optical depth. Based on multi-spectral optical aerosol depth, particle-size distribution and refractive index are derived by normalizing first- and second-order derivatives for processing quantitative calibration of main components. According to the optical feature parameters of various aerosol types, a radiation theory is applied to simulate multi-spectral optical depth for each density, including those of mixed types. The intrinsic parameters of aerosol types are figured out by constructing normalized derivative aerosol indices (NDAI). The clear characteristic differences between aerosol types are used to figure out main components of aerosols and their mixing ratios. The simulation result of the normalized index of various aerosol type is in good agreement with the ground observation data of Aerosol Robotic Network. It shows that NDAI is quite practicable in quantitative calibration of main components of atmospheric aerosol.

Abstract: A chemical mechanical polishing (CMP) slurry composition includes an oxidant including oxygen, and an abrasive particle having a core structure encapsulated by a shell structure. The core structure includes a first compound and the shell structure includes a second compound different from the first compound, where a diameter of the core structure is greater than a thickness of the shell structure, and where the first compound is configured to react with the oxidant to form a reactive oxygen species.

Abstract: A MRI-guided stereotactic surgery method including the following steps: assigning coordinates of a surgery target point of a surgery cannula and an insertion direction of the surgery cannula; performing coordinate transformation to transform the coordinates of the surgery target point into an insertion position of the surgery target point; substituting the insertion position and the insertion direction into an inverse kinematics model to obtain five parameters respectively corresponding to five degrees of freedom of a MRI-compatible stereotactic surgery device; controlling the MRI-compatible stereotactic surgery device according to the parameters to start a stereotactic surgery procedure, thereby inserting the surgery cannula; obtaining an actual cannula position according to a magnetic resonance (MR) image; comparing the actual cannula position with the surgery target point to obtain an actual position vector; and withdrawing the surgery cannula to finish the stereotactic surgery procedure when the actual po

Abstract: Some implementations described herein provide a method. The method includes forming a channel structure of a transistor. The method includes forming a work function metal (WFM), that includes aluminum and carbon, around the channel structure. Forming the WFM around the channel structure includes applying a chemical soak, with a material of the chemical soak including an aluminum, carbon, and hydrogen based material. The WFM includes a concentration of titanium that is in a range of 0% to less than 1.5% of the WFM. Some implementations described herein provide a transistor. The transistor includes a channel structure and an aluminum carbide (AlC)-based work function material (WFM) disposed around the channel structure. The WFM comprises a concentration of titanium that is in a range of 0% to less than 1.5% of the WFM.

Abstract: A heat transfer member reinforcement structure includes a main body. The main body has a first side, a second side and a reinforcement member. The reinforcement member is selectively disposed between the first and second sides or inlaid in a sink formed on the first side. The reinforcement member is connected with the main body to enhance the structural strength of the main body.

Abstract: The present disclosure describes a semiconductor device that includes a substrate and a first transistor on the substrate. The first transistor includes a first gate structure and the first gate structure includes a gate dielectric layer and a first work function layer on the gate dielectric layer. The first gate structure also includes a capping layer on the first work function layer. The semiconductor device also includes a second transistor on the substrate, in which the second transistor includes a second gate structure. The second gate structure includes the gate dielectric layer and a second work function layer on the gate dielectric layer. The second gate structure also includes the first work function layer on the second work function layer and the silicon capping layer on the first work function layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first source/drain epitaxial feature formed over a substrate, a second source/drain epitaxial feature formed over the substrate, two or more semiconductor layers disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a gate electrode layer surrounding a portion of one of the two or more semiconductor layers, a first dielectric region disposed in the substrate and in contact with a first side of the first source/drain epitaxial feature, and a second dielectric region disposed in the substrate and in contact with a first side of the second source/drain epitaxial feature, the second dielectric region being separated from the first dielectric region by a substrate.

Abstract: A semiconductor substrate has an exposed surface having a compositionally uniform metal, and an embedded surface having the metal and an oxide. The exposed surface is polished using a first slurry including a first abrasive and a first amine-based alkaline until the embedded surface is exposed. The embedded surface is polished using a second slurry including a second abrasive and a second amine-based alkaline. The second abrasive is different from the first abrasive. The second amine-based alkaline is different from the first amine-based alkaline. The metal and the oxide each has a first and a second removal rate in the first slurry, respectively, and a third and fourth removal rate in the second slurry, respectively. A ratio of the first removal rate to the second removal rate is greater than 30:1, and a ratio of the third removal rate to the fourth removal rate is about 1:0.5 to about 1:2.

Abstract: A method includes forming a plurality of nanostructures over a substrate; etching the plurality of nanostructures to form recesses; forming source/drain regions in the recesses; removing first nanostructures of the plurality of nanostructures leaving second nanostructures of the plurality of nanostructures; depositing a gate dielectric over and around the second nano structures; depositing a protective material over the gate dielectric; performing a fluorine treatment on the protective material; removing the protective material; and depositing a first conductive material over the gate dielectric; and depositing a second conductive material over the first conductive material.

Abstract: The present disclosure describes a semiconductor device that includes a substrate and a first transistor on the substrate. The first transistor includes a first gate structure and the first gate structure includes a gate dielectric layer and a first work function layer on the gate dielectric layer. The first gate structure also includes a capping layer on the first work function layer. The semiconductor device also includes a second transistor on the substrate, in which the second transistor includes a second gate structure. The second gate structure includes the gate dielectric layer and a second work function layer on the gate dielectric layer. The second gate structure also includes the first work function layer on the second work function layer and the silicon capping layer on the first work function layer.

Abstract: A genomic data decoder may jointly compress and encrypt genomic data alignment information while preserving the privacy of sensitive genomic data elements at retrieval stage. Genomic data alignment information organized as a read-based alignment data stream may be transposed into a position-based alignment data stream. The position-based alignment information may be encoded into a reference-based alignment data stream. The reference-based alignment data stream may be encrypted with a combination of order-preserving encryption of the genomic position information and symmetric encryption of the reference-based alignment differential data. Differential encoding and entropy coding schemes may further compress the reference-based alignment data stream. The resulting compressed and encrypted stream may be indexed and stored in a biobank storage unit.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first and second transistors arranged over a substrate. The first transistor includes first channel structures extending between first and second source/drain regions. A first gate electrode is arranged between the first channel structures, and a first protection layer is arranged over a topmost one of the first channel structures. The second transistor includes second channel structures extending between the second source/drain region and a third source/drain region. A second gate electrode is arranged between the second channel structures, and a second protection layer is arranged over a topmost one of the second channel structures. The integrated chip further includes a first interconnect structure arranged between the substrate and the first and second channel structures, and a contact plug structure coupled to the second source/drain region and arranged above the first and second gate electrodes.

Abstract: A method of forming a transistor is disclosed. The method includes forming a high-k dielectric constant layer on a semiconductor substrate, forming a pretreatment layer (PL) on the high-k dielectric constant layer, determining a thickness for a conductive work function layer (WFL) based on a target effective work function of the transistor, and forming the conductive work function layer (WFL) on the first pretreatment layer, where the conductive work function layer has a WFL thickness substantially equal to the determined thickness. Forming the transistor also includes forming a coating layer on the first conductive work function layer. The gate stack has a tuned effective work function according to the determined thickness.

Abstract: A semiconductor device includes a semiconductor substrate, an interfacial layer formed on the semiconductor substrate, a high-k dielectric layer formed on the interfacial layer, and a conductive gate electrode layer formed on the high-k dielectric layer. At least one of the high-k dielectric layer and the interfacial layer is doped with: a first dopant species, a second dopant species, and a third dopant species. The first dopant species and the second dopant species form a plurality of first dipole elements having a first polarity. The third dopant species forms a plurality of second dipole elements having a second polarity, and the first and second polarities are opposite.