Patents by Inventor Hyun-Jin Cho

Hyun-Jin Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160190207
    Abstract: Integrated circuits that include a magnetic tunnel junction (MTJ) for a magnetoresistive random-access memory (MRAM) and methods for fabricating such integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a lower electrode on a metal interconnect. The metal interconnect is disposed above a semiconductor substrate and is aligned with a normal axis that is substantially perpendicular to the semiconductor substrate. The lower electrode includes a conductive metal plug. A MTJ stack is formed on the lower electrode aligned with the normal axis.
    Type: Application
    Filed: June 24, 2015
    Publication date: June 30, 2016
    Inventors: Seowoo Nam, Ming He, Craig Child, Hyun-Jin Cho
  • Publication number: 20160141489
    Abstract: A method of forming a self-aligned MTJ without using a photolithography mask and the resulting device are provided. Embodiments include forming a first electrode over a metal layer, the metal layer recessed in a low-k dielectric layer; forming a MTJ layer over the first electrode; forming a second electrode over the MTJ layer; removing portions of the second electrode, the MTJ layer, and the first electrode down to the low-k dielectric layer; forming a silicon nitride-based layer over the second electrode and the low-k dielectric layer; and planarizing the silicon nitride-based layer down to the second electrode.
    Type: Application
    Filed: September 1, 2015
    Publication date: May 19, 2016
    Inventors: Xunyuan ZHANG, Ruilong XIE, Xiuyu CAI, Seowoo NAM, Hyun-Jin CHO
  • Patent number: 9269712
    Abstract: A method for making a semiconductor device may include forming a first semiconductor layer on a substrate comprising a first semiconductor material, forming a second semiconductor layer on the first semiconductor layer comprising a second semiconductor material, and forming mask regions on the second semiconductor layer and etching through the first and second semiconductor layers to define a plurality of spaced apart pillars on the substrate. The method may further include forming an oxide layer laterally surrounding the pillars and mask regions, and removing the mask regions and forming inner spacers on laterally adjacent corresponding oxide layer portions atop each pillar. The method may additionally include etching through the second semiconductor layer between respective inner spacers to define a pair of semiconductor fins of the second semiconductor material from each pillar, and removing the inner spacers and forming an oxide beneath each semiconductor fin.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: February 23, 2016
    Assignees: STMICROELECTRONICS, INC., GLOBALFOUNDRIES INC
    Inventors: Qing Liu, Ruilong Xie, Hyun-Jin Cho
  • Patent number: 9236557
    Abstract: Embodiments herein provide a magnetic tunnel junction (MTJ) formed between metal layers of a semiconductor device. Specifically, provided is an approach for forming the semiconductor device using only one or two masks, the approach comprising: forming a first metal layer in a dielectric layer of the semiconductor device, forming a bottom electrode layer over the first metal layer, forming a MTJ over the bottom electrode layer, forming a top electrode layer over the MTJ, patterning the top electrode layer and the MTJ with a first mask, and forming a second metal layer over the top electrode layer. Optionally, the bottom electrode layer may be patterned using a second mask. Furthermore, in another embodiment, an insulator layer (e.g., manganese) is formed atop the dielectric layer, wherein a top surface of the first metal layer remains exposed following formation of the insulator layer such that the bottom electrode layer contacts the top surface of the first metal layer.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: January 12, 2016
    Assignee: GlobalFoundries Inc.
    Inventors: Xunyuan Zhang, Ruilong Xie, Xiuyu Cai, Hyun-Jin Cho
  • Patent number: 9229148
    Abstract: A light guide plate includes a light incident surface, a light facing surface facing the light incident surface, a connection surface connecting the light incident surface with the light facing surface, and a top surface connected with the light incident surface, the light facing surface, and the connection surface. The light incident surface receives light from a light source, the light facing surface reflects light, and the top surface outputs light toward a display panel. The connection surface includes at least two absorption surfaces parallel to a straight line linking a center of an arc with an end of the light incident surface and at least one reflective surface interposed the two adjacent absorption surfaces to reflect the light.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: January 5, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hyun Jin Cho, Byoungho Cheong, Prudnikov Oleg, Hyundeok Im
  • Publication number: 20150348782
    Abstract: An apparatus for crystallizing an active layer of a thin film transistor, the apparatus includes a first laser irradiating a first beam toward a substrate, an amorphous layer on the substrate being crystallizable into the active layer of the thin film transistor by the first beam, and a second laser irradiating a second beam toward the substrate to heat the active layer, the second beam having an asymmetric intensity profile in a scanning direction of the first and second beams.
    Type: Application
    Filed: January 20, 2015
    Publication date: December 3, 2015
    Inventors: Byoung-Kwon CHOO, Sang-Hoon AHN, Byoung-Ho CHEONG, Joo-Woan CHO, Hyun-Jin CHO, Soo-Yeon HAN
  • Publication number: 20150340491
    Abstract: Approaches for spacer chamfering in a replacement metal gate (RMG) device are provided. Specifically, a semiconductor device is provided with a set of fins formed from a substrate; a silicon-based layer conformally deposited over the set of fins; an etch-stop layer (e.g., titanium nitride (TiN)) formed over the silicon-based layer, the etch-stop layer being selective to at least one of: silicon, oxide, and nitride; a set of RMG structures formed over the substrate; a set of spacers formed along each of the set of RMG structures, wherein a vertical layer of material from each of the set of spacers is removed selective to the etch-stop layer. By chamfering each sidewall spacer, a wider area for subsequent work-function (WF) metal deposition is provided. Meanwhile, each transistor channel region is covered by the etch-stop layer (e.g., TiN), which maintains the original gate critical dimension during reactive ion etching.
    Type: Application
    Filed: July 30, 2015
    Publication date: November 26, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Hui Zang, Hyun-Jin Cho
  • Patent number: 9190260
    Abstract: A method of forming a self-aligned MTJ without using a photolithography mask and the resulting device are provided. Embodiments include forming a first electrode over a metal layer, the metal layer recessed in a low-k dielectric layer; forming a MTJ layer over the first electrode; forming a second electrode over the MTJ layer; removing portions of the second electrode, the MTJ layer, and the first electrode down to the low-k dielectric layer; forming a silicon nitride-based layer over the second electrode and the low-k dielectric layer; and planarizing the silicon nitride-based layer down to the second electrode.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: November 17, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xunyuan Zhang, Ruilong Xie, Xiuyu Cai, Seowoo Nam, Hyun-Jin Cho
  • Publication number: 20150318178
    Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial gate structure above a semiconductor substrate, forming a sidewall spacer adjacent opposite sides of the sacrificial gate structure, removing the sacrificial gate structure and forming a replacement gate structure in its place, at some point after forming the replacement gate structure, performing an etching process to reduce the height of the spacers so as to thereby define recessed spacers having an upper surface that partially defines a spacer recess, and forming a spacer etch block cap on the upper surface of each recessed spacer structure and within the spacer recess.
    Type: Application
    Filed: May 2, 2014
    Publication date: November 5, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Daniel T. Pham, Hyun-Jin Cho, Ruilong Xie
  • Patent number: 9129986
    Abstract: Approaches for spacer chamfering in a replacement metal gate (RMG) device are provided. Specifically, a semiconductor device is provided with a set of fins formed from a substrate; a silicon-based layer conformally deposited over the set of fins; an etch-stop layer (e.g., titanium nitride (TiN)) formed over the silicon-based layer, the etch-stop layer being selective to at least one of: silicon, oxide, and nitride; a set of RMG structures formed over the substrate; a set of spacers formed along each of the set of RMG structures, wherein a vertical layer of material from each of the set of spacers is removed selective to the etch-stop layer. By chamfering each sidewall spacer, a wider area for subsequent work-function (WF) metal deposition is provided. Meanwhile, each transistor channel region is covered by the etch-stop layer (e.g., TiN), which maintains the original gate critical dimension during reactive ion etching.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: September 8, 2015
    Assignee: GlobalFoundries Inc.
    Inventors: Hui Zang, Hyun-Jin Cho
  • Patent number: 9105559
    Abstract: A conformal doping process for FinFET devices on a semiconductor substrate which includes NFET fins and PFET fins. In a first exemplary embodiment, an N-type dopant composition is conformally deposited over the NFET fins and the PFET fins. The semiconductor substrate is annealed to drive in an N-type dopant from the N-type dopant composition into the NFET fins. A P-type dopant composition is conformally deposited over the NFET fins and the PFET fins. The semiconductor substrate is annealed to drive in a P-type dopant from the P-type dopant composition into the PFET fins. In a second exemplary embodiment, one of the NFET fins and PFET fins may be covered with a first dopant composition and then a second dopant composition may cover both the NFET fins and the PFET fins followed by an anneal to drive in both dopants.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: August 11, 2015
    Assignees: International Business Machines Corporation, Global Foundries, Inc.
    Inventors: Veeraraghavan S. Basker, Nathaniel Berliner, Hyun-Jin Cho, Johnathan Faltermeier, Kam-Leung Lee, Tenko Yamashita
  • Publication number: 20150200353
    Abstract: Embodiments herein provide a magnetic tunnel junction (MTJ) formed between metal layers of a semiconductor device. Specifically, provided is an approach for forming the semiconductor device using only one or two masks, the approach comprising: forming a first metal layer in a dielectric layer of the semiconductor device, forming a bottom electrode layer over the first metal layer, forming a MTJ over the bottom electrode layer, forming a top electrode layer over the MTJ, patterning the top electrode layer and the MTJ with a first mask, and forming a second metal layer over the top electrode layer. Optionally, the bottom electrode layer may be patterned using a second mask. Furthermore, in another embodiment, an insulator layer (e.g., manganese) is formed atop the dielectric layer, wherein a top surface of the first metal layer remains exposed following formation of the insulator layer such that the bottom electrode layer contacts the top surface of the first metal layer.
    Type: Application
    Filed: January 15, 2014
    Publication date: July 16, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Xunyuan Zhang, Ruilong Xie, Xiuyu Cai, Hyun-Jin Cho
  • Publication number: 20150115370
    Abstract: A method for making a semiconductor device may include forming a first semiconductor layer on a substrate comprising a first semiconductor material, forming a second semiconductor layer on the first semiconductor layer comprising a second semiconductor material, and forming mask regions on the second semiconductor layer and etching through the first and second semiconductor layers to define a plurality of spaced apart pillars on the substrate. The method may further include forming an oxide layer laterally surrounding the pillars and mask regions, and removing the mask regions and forming inner spacers on laterally adjacent corresponding oxide layer portions atop each pillar. The method may additionally include etching through the second semiconductor layer between respective inner spacers to define a pair of semiconductor fins of the second semiconductor material from each pillar, and removing the inner spacers and forming an oxide beneath each semiconductor fin.
    Type: Application
    Filed: October 31, 2013
    Publication date: April 30, 2015
    Applicants: GLOBALFOUNDRIES Inc., STMicroelectronics, Inc.
    Inventors: Qing LIU, Ruilong Xie, Hyun-Jin Cho
  • Publication number: 20150079773
    Abstract: A conformal doping process for FinFET devices on a semiconductor substrate which includes NFET fins and PFET fins. In a first exemplary embodiment, an N-type dopant composition is conformally deposited over the NFET fins and the PFET fins. The semiconductor substrate is annealed to drive in an N-type dopant from the N-type dopant composition into the NFET fins. A P-type dopant composition is conformally deposited over the NFET fins and the PFET fins. The semiconductor substrate is annealed to drive in a P-type dopant from the P-type dopant composition into the PFET fins. In a second exemplary embodiment, one of the NFETfins and PFET fins may be covered with a first dopant composition and then a second dopant composition may cover both the NFET fins and the PFET fins followed by an anneal to drive in both dopants.
    Type: Application
    Filed: September 16, 2013
    Publication date: March 19, 2015
    Applicants: GLOBALFOUNDRIES Inc., International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Nathaniel Berliner, Hyun-Jin Cho, Johnathan Faltermeler, Kam-Leung Lee, Tenko Yamashita
  • Patent number: 8941799
    Abstract: Provided is a liquid crystal display including: a lower display panel including a lower insulating substrate and a lower reflective layer; an upper display panel including an upper insulating substrate and an upper reflective layer; a liquid crystal layer positioned between the lower reflective layer of the lower display panel and the upper reflective layer of the upper display panel; and a backlight unit positioned on a lower portion of the lower display panel and including a light source, wherein a pair of field generating electrodes are formed in at least one display panel of the lower display panel and the upper display panel, wherein microcavities are formed in the lower reflective layer, the upper reflective layer, and the liquid crystal layer, and wherein a wavelength and luminance of light resonated and emitted in the microcavities are changed by an electric field generated by the field generating electrodes.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: January 27, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jae Ho You, Hyun Jin Cho, Dae Ho Yoon, Moon Gyu Lee, Byoung Ho Cheong
  • Publication number: 20150001627
    Abstract: Approaches for spacer chamfering in a replacement metal gate (RMG) device are provided. Specifically, a semiconductor device is provided with a set of fins formed from a substrate; a silicon-based layer conformally deposited over the set of fins; an etch-stop layer (e.g., titanium nitride (TiN)) formed over the silicon-based layer, the etch-stop layer being selective to at least one of: silicon, oxide, and nitride; a set of RMG structures formed over the substrate; a set of spacers formed along each of the set of RMG structures, wherein a vertical layer of material from each of the set of spacers is removed selective to the etch-stop layer. By chamfering each sidewall spacer, a wider area for subsequent work-function (WF) metal deposition is provided. Meanwhile, each transistor channel region is covered by the etch-stop layer (e.g., TiN), which maintains the original gate critical dimension during reactive ion etching.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: Hui Zang, Hyun-Jin Cho
  • Publication number: 20140361298
    Abstract: Disclosed is a novel system and method to form local interconnects in a continuity test structure. The method begins with a first set of transistor gate lines and a second set of transistor gate lines are formed. Next, a first group of two or more local interconnect lines landing on transistor gates and formed substantially perpendicular to the first set of transistor gate lines and electrically coupled therewith is formed using a first lithography pass. A second group of two or more local interconnect lines landing and formed substantially perpendicular to the second set of transistor gate lines and electrically coupled therewith is formed during second lithography pass. For some technologies, a third set of transistor gate lines is formed along with a third group using a third lithography pass.
    Type: Application
    Filed: June 7, 2013
    Publication date: December 11, 2014
    Inventors: Hyun-Jin CHO, Tenko YAMASHITA, Chun-chen YEH, Hui ZANG
  • Patent number: 8819790
    Abstract: The present invention relates to a method of embodying a cooperation system between SEND and IPSec in an IPv6 environment. The cooperation system between SEND and IPSec in accordance with the present invention includes: receiving an authentication completion report message including a first IP address of a host whose authentication is completed by the SEND; generating new authentication information corresponding to the host and storing the new authentication information in a temporary storage area, if authentication information for the host is not present in the temporary storage area, wherein the authentication information includes the first IP address; and if an authentication check request message including a second IP address is received from the IPSec, checking whether the second IP address is present in the temporary storage area, and sending the result of checking to the IPSec.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: August 26, 2014
    Assignee: Sungkyunkwan University Foundation for Corporate Collaboration
    Inventors: Young-Ik Eom, Kwang-Sun Ko, Hyun-Su Jang, Hyun-jin Cho, Yong-Woo Jung, Hyun-Woo Choi, Gye-Hyeon Gyeong, Jung-Hwan Choi, Zhen Zhao, Tae-Hyoung Kim, Youn-Woo Kim
  • Patent number: 8753881
    Abstract: The present invention relates to a method for differentiation of mesenchymal stem cells. More specifically, the invention relates to a method for differentiating mesenchymal stem cells to neural cells by treating the mesenchymal stem cells with low-frequency sound waves. The differentiation method of the present invention can induce differentiation even with low-cost media rather than induced neural differentiation mediums which are expensive due to addition of growth factors, and the neural cells differentiated according to the present invention may be useful for treatment of neurological diseases.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: June 17, 2014
    Assignee: Dongguk University Industry-Academic Cooperation Foundation
    Inventors: Jung-Keug Park, Moon Young Yoon, Hyun Jin Cho, Young-Kwon Seo, Song Hee Jeon, Hee Hoon Yoon
  • Publication number: 20140146564
    Abstract: A backlight unit includes a light source part, a light guide plate, a prism sheet, and a reflecting element. The light source part is configured to provide light. The light guide plate includes: a light incident portion disposed adjacent to the light source part, a corresponding portion spaced apart from and facing the light incident portion, a light exiting surface, and a bottom surface spaced apart from and facing the light exiting surface. A thickness of the light incident portion is greater than a thickness of the corresponding portion. The prism sheet is disposed on the light guide plate. The prism sheet includes a plurality of prisms extending toward the light guide plate. The reflecting element is disposed under the light guide plate. The reflecting element is configured to reflect at least some of the light toward the light guide plate.
    Type: Application
    Filed: August 21, 2013
    Publication date: May 29, 2014
    Applicant: Samsung Display Co., Ltd.
    Inventors: Hyun-Deok IM, Oleg Prudnikov, Byoung-Ho Cheong, Hyun-Jin Cho, Guk-Hyun Kim