Patents by Inventor Ian P. Shaeffer

Ian P. Shaeffer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8504788
    Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command if a time interval since a last read command issued by the memory controller exceeds a predetermined value.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: August 6, 2013
    Assignee: Rambus Inc.
    Inventors: Bret Stott, Frederick A. Ware, Ian P. Shaeffer, Yuanlong Wang
  • Publication number: 20130148447
    Abstract: Components of a memory system, such as a memory controller or memory device, that operate in different power states to reduce the overall power consumption of the memory system. In some of the power states, distribution circuitry that distributes a timing signal within the components may be powered on when the output of the distribution circuitry is needed. In other power states, the distribution circuitry may be powered off when the output of the distribution circuitry is not needed. Additionally, power states in the memory device may be triggered off memory access commands issued by the memory controller.
    Type: Application
    Filed: December 6, 2012
    Publication date: June 13, 2013
    Inventors: Ian P. Shaeffer, Jared L. Zerbe, Frederick A. Ware
  • Patent number: 8380943
    Abstract: A memory module having a plurality of memory devices and a memory buffer that translates between a variable width primary data port and a plurality of fixed width secondary data ports, each of which is coupled to one of the memory devices. The translation is effected by distributing the width of the primary data port to all or to a subset of the secondary data ports. In another aspect, the invention comprises a memory buffer that supports adjustable data width in a variety of ways.
    Type: Grant
    Filed: January 7, 2009
    Date of Patent: February 19, 2013
    Assignee: Rambus Inc.
    Inventor: Ian P. Shaeffer
  • Patent number: 8344475
    Abstract: In a system having a memory device, an event is detected during system operation. The memory device is heated to reverse use-incurred degradation of the memory device in response to detecting the event. In another system, the memory device is heated to reverse use-incurred degradation concurrently with execution of a data access operation within another memory device of the system. In another system having a memory controller coupled to first and second memory devices, data is evacuated from the first memory device to the second memory device in response to determining that a maintenance operation is needed within the first memory device.
    Type: Grant
    Filed: August 19, 2010
    Date of Patent: January 1, 2013
    Assignee: Rambus Inc.
    Inventors: Ian P. Shaeffer, Gary B. Bronner, Brent S. Haukness, Kevin S. Donnelly, Frederick A. Ware, Mark A. Horowitz
  • Patent number: 8339878
    Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: December 25, 2012
    Assignee: Rambus Inc.
    Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
  • Publication number: 20120265930
    Abstract: An integrated circuit device transmits, to a dynamic random access memory device (DRAM), a write command indicating that write data is to be sampled by a data interface of the DRAM, and a plurality of commands that specify programming a plurality of control values into a plurality of corresponding registers in the DRAM. The plurality of control values include first and second control values that indicate respective first and second terminations that the DRAM is to apply to the data interface during a time interval that begins a predetermined amount of time after the DRAM receives the write command, the first termination to be applied during a first portion of the time interval while the data interface is sampling the write data and the second termination to be applied during a second portion of the time interval after the write data is sampled.
    Type: Application
    Filed: May 24, 2012
    Publication date: October 18, 2012
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Publication number: 20120188835
    Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
    Type: Application
    Filed: December 23, 2011
    Publication date: July 26, 2012
    Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
  • Patent number: 8188762
    Abstract: A control component outputs to an integrated circuit device an indication to apply one of a plurality of controllable termination impedance configurations at a data input of the integrated circuit device. The indication causes the integrated circuit device to apply a first of the controllable termination impedance configurations at the data input during a first internal state of the integrated circuit device corresponding to the reception of write data on the data input, and causes the integrated circuit device to apply a second of the controllable termination impedance configurations at the data input during a second internal state of the integrated circuit device that follows the first internal state.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: May 29, 2012
    Assignee: Rambus Inc.
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Patent number: 8089298
    Abstract: In an integrated circuit device having dynamically selected on-die termination, a set of data inputs are coupled respectively to a set of termination circuits, each termination circuit having multiple controllable termination impedance configurations.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: January 3, 2012
    Assignee: Rambus Inc.
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Patent number: 8089824
    Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: January 3, 2012
    Assignee: Rambus Inc.
    Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
  • Publication number: 20110299317
    Abstract: In a system having a memory device, an event is detected during system operation. The memory device is heated to reverse use-incurred degradation of the memory device in response to detecting the event. In another system, the memory device is heated to reverse use-incurred degradation concurrently with execution of a data access operation within another memory device of the system. In another system having a memory controller coupled to first and second memory devices, data is evacuated from the first memory device to the second memory device in response to determining that a maintenance operation is needed within the first memory device.
    Type: Application
    Filed: August 19, 2010
    Publication date: December 8, 2011
    Inventors: Ian P. Shaeffer, Gary B. Bronner, Brent S. Haukness, Kevin S. Donnelly, Frederick A. Ware, Mark A. Horowitz
  • Publication number: 20110267101
    Abstract: A control component outputs to an integrated circuit device an indication to apply one of a plurality of controllable termination impedance configurations at a data input of the integrated circuit device. The indication causes the integrated circuit device to apply a first of the controllable termination impedance configurations at the data input during a first internal state of the integrated circuit device corresponding to the reception of write data on the data input, and causes the integrated circuit device to apply a second of the controllable termination impedance configurations at the data input during a second internal state of the integrated circuit device that follows the first internal state.
    Type: Application
    Filed: July 12, 2011
    Publication date: November 3, 2011
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Publication number: 20110248407
    Abstract: Multiple devices, including a first device and a second device, have operational circuitry and opposing first and second surfaces. First and second electrical contacts are formed at the first surface, while a third electrical contact is formed at the second surface opposite the first electrical contact. The first electrical contact is electrically connected to the operational circuitry, and the second electrical contact is electrically connected to the third electrical contact. The first device and the second device are subsequently stacked such that the first surface of the second device is located adjacent the second surface of the first device such that the first electrical contact of the second device is aligned with the third electrical contact of the first device. The first electrical contact of the second device is electrically connected to the third electrical contact of the first device.
    Type: Application
    Filed: June 23, 2011
    Publication date: October 13, 2011
    Inventors: Frederick A. Ware, Ely K. Tsern, Ian P. Shaeffer
  • Publication number: 20110241727
    Abstract: In an integrated circuit device having dynamically selected on-die termination, a set of data inputs are coupled respectively to a set of termination circuits, each termination circuit having multiple controllable termination impedance configurations.
    Type: Application
    Filed: June 14, 2011
    Publication date: October 6, 2011
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Patent number: 7989265
    Abstract: Multiple devices, including a first device and a second device, have operational circuitry and opposing first and second surfaces. First and second electrical contacts are formed at the first surface, while a third electrical contact is formed at the second surface opposite the first electrical contact. The first electrical contact is electrically connected to the operational circuitry, and the second electrical contact is electrically connected to the third electrical contact. The first device and the second device are subsequently stacked such that the first surface of the second device is located adjacent the second surface of the first device such that the first electrical contact of the second device is aligned with the third electrical contact of the first device. The first electrical contact of the second device is electrically connected to the third electrical contact of the first device.
    Type: Grant
    Filed: January 28, 2009
    Date of Patent: August 2, 2011
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Ely K. Tsern, Ian P. Shaeffer
  • Publication number: 20110156750
    Abstract: In an integrated circuit device having dynamically selected on-die termination, a set of data inputs are coupled respectively to a set of termination circuits, each termination circuit having multiple controllable termination impedance configurations.
    Type: Application
    Filed: March 9, 2011
    Publication date: June 30, 2011
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Publication number: 20110138133
    Abstract: A memory module having a plurality of memory devices and a memory buffer that translates between a variable width primary data port and a plurality of fixed width secondary data ports, each of which is coupled to one of the memory devices. The translation is effected by distributing the width of the primary data port to all or to a subset of the secondary data ports. In another aspect, the invention comprises a memory buffer that supports adjustable data width in a variety of ways.
    Type: Application
    Filed: January 7, 2009
    Publication date: June 9, 2011
    Inventor: Ian P. Shaeffer
  • Patent number: 7924048
    Abstract: A memory controller that controls termination in a memory device. The memory controller includes a data interface, command/address interface and termination control output. The data interface outputs write data onto a data line coupled to a data input of the memory device, and the command/address interfaces outputs, onto a command/address path coupled to the memory device, information that indicates whether the write data is to be received within the memory device.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: April 12, 2011
    Assignee: Rambus Inc.
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Publication number: 20100315122
    Abstract: A memory controller that controls termination in a memory device. The memory controller includes a data interface, command/address interface and termination control output. The data interface outputs write data onto a data line coupled to a data input of the memory device, and the command/address interfaces outputs, onto a command/address path coupled to the memory device, information that indicates whether the write data is to be received within the memory device.
    Type: Application
    Filed: August 23, 2010
    Publication date: December 16, 2010
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Patent number: 7782082
    Abstract: In memory module having multiple data inputs to couple to signal lines of an external data path, multiple memory integrated-circuits (ICs) and a buffer IC, the buffer IC includes respective interfaces coupled to the data inputs and the memory ICs, a first termination circuit having a first load element and a first switch element to switchably couple the first load element to a first data input of the data inputs and a second termination circuit having a second load element and a second switch element to switchably couple the second load element to the first data input. The buffer IC further includes a configuration circuit to store, in response to control information from a memory controller, a first digital value and a second digital value, the first digital value being supplied to the first termination circuit to control an impedance of the first load element and the second digital value being supplied to the second termination circuit to control an impedance of the second load element.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: August 24, 2010
    Assignee: Rambus Inc.
    Inventors: Kyung Suk Oh, Ian P. Shaeffer