Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

Abstract: In an integrated circuit device having dynamically selected on-die termination, a set of data inputs are coupled respectively to a set of termination circuits, each termination circuit having multiple controllable termination impedance configurations.

Abstract: In a system having a memory device, an event is detected during system operation. The memory device is heated to reverse use-incurred degradation of the memory device in response to detecting the event. In another system, the memory device is heated to reverse use-incurred degradation concurrently with execution of a data access operation within another memory device of the system. In another system having a memory controller coupled to first and second memory devices, data is evacuated from the first memory device to the second memory device in response to determining that a maintenance operation is needed within the first memory device.

Abstract: A control component outputs to an integrated circuit device an indication to apply one of a plurality of controllable termination impedance configurations at a data input of the integrated circuit device. The indication causes the integrated circuit device to apply a first of the controllable termination impedance configurations at the data input during a first internal state of the integrated circuit device corresponding to the reception of write data on the data input, and causes the integrated circuit device to apply a second of the controllable termination impedance configurations at the data input during a second internal state of the integrated circuit device that follows the first internal state.

Abstract: Multiple devices, including a first device and a second device, have operational circuitry and opposing first and second surfaces. First and second electrical contacts are formed at the first surface, while a third electrical contact is formed at the second surface opposite the first electrical contact. The first electrical contact is electrically connected to the operational circuitry, and the second electrical contact is electrically connected to the third electrical contact. The first device and the second device are subsequently stacked such that the first surface of the second device is located adjacent the second surface of the first device such that the first electrical contact of the second device is aligned with the third electrical contact of the first device. The first electrical contact of the second device is electrically connected to the third electrical contact of the first device.

Abstract: In an integrated circuit device having dynamically selected on-die termination, a set of data inputs are coupled respectively to a set of termination circuits, each termination circuit having multiple controllable termination impedance configurations.

Abstract: Multiple devices, including a first device and a second device, have operational circuitry and opposing first and second surfaces. First and second electrical contacts are formed at the first surface, while a third electrical contact is formed at the second surface opposite the first electrical contact. The first electrical contact is electrically connected to the operational circuitry, and the second electrical contact is electrically connected to the third electrical contact. The first device and the second device are subsequently stacked such that the first surface of the second device is located adjacent the second surface of the first device such that the first electrical contact of the second device is aligned with the third electrical contact of the first device. The first electrical contact of the second device is electrically connected to the third electrical contact of the first device.

Abstract: In an integrated circuit device having dynamically selected on-die termination, a set of data inputs are coupled respectively to a set of termination circuits, each termination circuit having multiple controllable termination impedance configurations.

Abstract: A memory module having a plurality of memory devices and a memory buffer that translates between a variable width primary data port and a plurality of fixed width secondary data ports, each of which is coupled to one of the memory devices. The translation is effected by distributing the width of the primary data port to all or to a subset of the secondary data ports. In another aspect, the invention comprises a memory buffer that supports adjustable data width in a variety of ways.

Abstract: A memory controller that controls termination in a memory device. The memory controller includes a data interface, command/address interface and termination control output. The data interface outputs write data onto a data line coupled to a data input of the memory device, and the command/address interfaces outputs, onto a command/address path coupled to the memory device, information that indicates whether the write data is to be received within the memory device.

Abstract: A memory controller that controls termination in a memory device. The memory controller includes a data interface, command/address interface and termination control output. The data interface outputs write data onto a data line coupled to a data input of the memory device, and the command/address interfaces outputs, onto a command/address path coupled to the memory device, information that indicates whether the write data is to be received within the memory device.

Abstract: In memory module having multiple data inputs to couple to signal lines of an external data path, multiple memory integrated-circuits (ICs) and a buffer IC, the buffer IC includes respective interfaces coupled to the data inputs and the memory ICs, a first termination circuit having a first load element and a first switch element to switchably couple the first load element to a first data input of the data inputs and a second termination circuit having a second load element and a second switch element to switchably couple the second load element to the first data input. The buffer IC further includes a configuration circuit to store, in response to control information from a memory controller, a first digital value and a second digital value, the first digital value being supplied to the first termination circuit to control an impedance of the first load element and the second digital value being supplied to the second termination circuit to control an impedance of the second load element.

Abstract: The point-to-point interconnection system for stacked devices includes a device, a substrate, operational circuitry, at least three electrical contacts and a conductor. The substrate has opposing first and second surfaces. A first electrical contact is mechanically coupled to the first surface of the device and electrically coupled to the operational circuitry. The second electrical contact is mechanically coupled to the first surface. The third electrical contact is mechanically coupled to the second surface opposite the first electrical contact. The conductor electrically couples the second electrical contact to the third electrical contact.

Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command if a time interval since a last read command issued by the memory controller exceeds a predetermined value.

Abstract: A system includes a plurality of memory devices arranged in a fly-by topology, each of the memory devices having on-die termination (ODT) circuitry for connection to an address and control (RQ) bus. The ODT circuitry has at least one input for controlling termination of one or more signal lines of the RQ bus. Application of a first logic level to the at least one input enables termination of the one or more signal lines. Application of a second logic level to the at least one input disables termination of the one or more signal lines.

Abstract: In memory module having multiple data inputs to couple to signal lines of an external data path, multiple memory integrated-circuits (ICs) and a buffer IC, the buffer IC includes respective interfaces coupled to the data inputs and the memory ICs, a first termination circuit having a first load element and a first switch element to switchably couple the first load element to a first data input of the data inputs and a second termination circuit having a second load element and a second switch element to switchably couple the second load element to the first data input. The buffer IC further includes a configuration circuit to store, in response to control information from a memory controller, a first digital value and a second digital value, the first digital value being supplied to the first termination circuit to control an impedance of the first load element and the second digital value being supplied to the second termination circuit to control an impedance of the second load element.

Abstract: A memory controller for controlling integrated circuit memory devices that have on-die termination. The memory controller includes an output driver to output a first data signal onto a data line, and termination control circuitry to output termination control signals to integrated circuit memory devices coupled to the data line. The termination control signals control coupling and decoupling of termination elements to the data line according to which of the plurality of integrated circuit memory devices is selected to receive the first data signal.

Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated with a phase offset relative to a first clock signal in accordance with a first programmed value, and a second timing signal is generated with a phase offset relative to the first clock signal in accordance with a second programmed value. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

Abstract: Multiple devices, including a first device and a second device, have operational circuitry and opposing first and second surfaces. First and second electrical contacts are formed at the first surface, while a third electrical contact is formed at the second surface opposite the first electrical contact. The first electrical contact is electrically connected to the operational circuitry, and the second electrical contact is electrically connected to the third electrical contact. The first device and the second device are subsequently stacked such that the first surface of the second device is located adjacent the second surface of the first device such that the first electrical contact of the second device is aligned with the third electrical contact of the first device. The first electrical contact of the second device is electrically connected to the third electrical contact of the first device.