Patents by Inventor Ian P. Shaeffer

Ian P. Shaeffer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7701045
    Abstract: The point-to-point interconnection system for stacked devices includes a device, a substrate, operational circuitry, at least three electrical contacts and a conductor. The substrate has opposing first and second surfaces. A first electrical contact is mechanically coupled to the first surface of the device and electrically coupled to the operational circuitry. The second electrical contact is mechanically coupled to the first surface. The third electrical contact is mechanically coupled to the second surface opposite the first electrical contact. The conductor electrically couples the second electrical contact to the third electrical contact.
    Type: Grant
    Filed: April 11, 2006
    Date of Patent: April 20, 2010
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Ely K. Tsern, Ian P. Shaeffer
  • Publication number: 20100039875
    Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command if a time interval since a last read command issued by the memory controller exceeds a predetermined value.
    Type: Application
    Filed: December 19, 2007
    Publication date: February 18, 2010
    Inventors: Bret Stott, Frederick A. Ware, Ian P. Shaeffer, Yuanlong Wang
  • Publication number: 20100027356
    Abstract: A system includes a plurality of memory devices arranged in a fly-by topology, each of the memory devices having on-die termination (ODT) circuitry for connection to an address and control (RQ) bus. The ODT circuitry has at least one input for controlling termination of one or more signal lines of the RQ bus. Application of a first logic level to the at least one input enables termination of the one or more signal lines. Application of a second logic level to the at least one input disables termination of the one or more signal lines.
    Type: Application
    Filed: December 19, 2007
    Publication date: February 4, 2010
    Inventors: Ian P. Shaeffer, Kyung S. Oh
  • Publication number: 20090284281
    Abstract: In memory module having multiple data inputs to couple to signal lines of an external data path, multiple memory integrated-circuits (ICs) and a buffer IC, the buffer IC includes respective interfaces coupled to the data inputs and the memory ICs, a first termination circuit having a first load element and a first switch element to switchably couple the first load element to a first data input of the data inputs and a second termination circuit having a second load element and a second switch element to switchably couple the second load element to the first data input. The buffer IC further includes a configuration circuit to store, in response to control information from a memory controller, a first digital value and a second digital value, the first digital value being supplied to the first termination circuit to control an impedance of the first load element and the second digital value being supplied to the second termination circuit to control an impedance of the second load element.
    Type: Application
    Filed: July 22, 2009
    Publication date: November 19, 2009
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Patent number: 7602209
    Abstract: A memory controller for controlling integrated circuit memory devices that have on-die termination. The memory controller includes an output driver to output a first data signal onto a data line, and termination control circuitry to output termination control signals to integrated circuit memory devices coupled to the data line. The termination control signals control coupling and decoupling of termination elements to the data line according to which of the plurality of integrated circuit memory devices is selected to receive the first data signal.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: October 13, 2009
    Assignee: Rambus Inc.
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Publication number: 20090238025
    Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
    Type: Application
    Filed: June 3, 2009
    Publication date: September 24, 2009
    Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
  • Patent number: 7558150
    Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated with a phase offset relative to a first clock signal in accordance with a first programmed value, and a second timing signal is generated with a phase offset relative to the first clock signal in accordance with a second programmed value. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
    Type: Grant
    Filed: June 25, 2007
    Date of Patent: July 7, 2009
    Assignee: Rambus Inc.
    Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
  • Publication number: 20090130798
    Abstract: Multiple devices, including a first device and a second device, have operational circuitry and opposing first and second surfaces. First and second electrical contacts are formed at the first surface, while a third electrical contact is formed at the second surface opposite the first electrical contact. The first electrical contact is electrically connected to the operational circuitry, and the second electrical contact is electrically connected to the third electrical contact. The first device and the second device are subsequently stacked such that the first surface of the second device is located adjacent the second surface of the first device such that the first electrical contact of the second device is aligned with the third electrical contact of the first device. The first electrical contact of the second device is electrically connected to the third electrical contact of the first device.
    Type: Application
    Filed: January 28, 2009
    Publication date: May 21, 2009
    Inventors: Frederick A. Ware, Ely K. Tsern, Ian P. Shaeffer
  • Patent number: 7486104
    Abstract: An integrated circuit device having graduated on-die termination. The integrated circuit device includes an input to receive a data signal, and first and second termination circuits. The first termination circuit includes a first load element and a first switch element to switchably couple the first load element to the data signal input. The second termination circuit includes a second load element and a second switch element to switchably couple the second load element to the data signal input.
    Type: Grant
    Filed: June 2, 2006
    Date of Patent: February 3, 2009
    Assignee: RAMBUS Inc.
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Publication number: 20080315916
    Abstract: A memory controller for controlling integrated circuit memory devices that have on-die termination. The memory controller includes an output driver to output a first data signal onto a data line, and termination control circuitry to output termination control signals to integrated circuit memory devices coupled to the data line. The termination control signals control coupling and decoupling of termination elements to the data line according to which of the plurality of integrated circuit memory devices is selected to receive the first data signal.
    Type: Application
    Filed: August 27, 2008
    Publication date: December 25, 2008
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Patent number: 7412923
    Abstract: A stencil device ensures that solder paste is accurately applied to a printed circuit board to create a substantially zero signal degradation solder bridge electrical connection. The printed circuit board is defined by a dielectric structure core having a first surface which further includes a first conducting pad having an edge and a second conducting edge having an edge separated from and adjacent to the edge of the first conducting pad. The edges of the first and second conducting pads define therebetween a surface area of the first surface. The stencil device includes a stencil plate member defining a first opening sized to substantially correspond to the first conducting pad, a second opening sized to substantially correspond to the second conducting pad, and a third opening. The third opening links the first opening to the second opening at a size to correspond to a partial portion of the surface area of the first surface between the edges of the first and second conducting pads.
    Type: Grant
    Filed: September 3, 2003
    Date of Patent: August 19, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Ian P. Shaeffer, Everett Basham, Christopher D. Price
  • Patent number: 7321524
    Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated with a phase offset relative to a first clock signal in accordance with a first programmed value, and a second timing signal is generated with a phase offset relative to the first clock signal in accordance with a second programmed value. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
    Type: Grant
    Filed: October 17, 2005
    Date of Patent: January 22, 2008
    Assignee: Rambus Inc.
    Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
  • Publication number: 20070279084
    Abstract: An integrated circuit device having graduated on-die termination. The integrated circuit device includes an input to receive a data signal, and first and second termination circuits. The first termination circuit includes a first load element and a first switch element to switchably couple the first load element to the data signal input. The second termination circuit includes a second load element and a second switch element to switchably couple the second load element to the data signal input.
    Type: Application
    Filed: June 2, 2006
    Publication date: December 6, 2007
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Patent number: 7196948
    Abstract: A method for reading data from a memory module over a bi-directional bus is provided. The method initiates with issuing a read command. Then, a strobe signal is transitioned from a mid-rail state. In one embodiment, the strobe signal is transitioned to a logical low state. A read enable signal is then transitioned prior to a first falling edge of the strobe signal. The strobe signal represents an earliest availability for valid read data being available. The valid read data is read in response to the read enable signal transition. A microprocessor and a system wherein data is read over a bi-directional bus are included.
    Type: Grant
    Filed: March 7, 2005
    Date of Patent: March 27, 2007
    Assignee: Sun Microsystems, Inc .
    Inventors: Sunil K. Vemula, Francis X. Schumacher, Ian P. Shaeffer
  • Patent number: 7140531
    Abstract: A method of fabricating a substantially zero signal degradation electrical connection on a printed circuit board includes providing a printed circuit board defined by a dielectric structure core. The dielectric structure core has a first surface, which includes a first connecting pad having an edge and a second connecting pad having an edge separated from an adjacent to the edge of the first conducting pad. The edges of the first and second conducting pads define therebetween a surface area of the first surface. A solder paste is applied on the first and second conducting pads and on the first surface of the dielectric structure core. The solder paste at least partially covers the surface area of the first surface between the edges of the first and second conducting pads, thereby forming a substantially zero signal degradation electrical connection between the first and second conducting pads.
    Type: Grant
    Filed: September 3, 2003
    Date of Patent: November 28, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Ian P. Shaeffer, Everett Basham, Christopher D. Price
  • Publication number: 20040041001
    Abstract: A method of fabricating a zero signal degradation solder bridge electrical connection for connecting adjacent conducting pads of a printed circuit board, and a printed circuit board having at least one of these solder bridge electrical connections. In the method, a stencil, having an opening that corresponds to the adjacent conducting pads and at least a portion of the surface area of the printed circuit board between the adjacent conducting pads, is placed on the surface of printed circuit board. Solder paste is then applied to the stencil such that the solder paste flows through the stencil opening and onto the adjacent conducting pads and at least a portion of the surface area of the printed circuit board between the pads. The stencil is then removed and the printed circuit board is subjected to reflow soldering, thereby fabricating a printed circuit board having a solder bridge electrical connector between adjacent conducting pads.
    Type: Application
    Filed: September 3, 2003
    Publication date: March 4, 2004
    Inventors: Ian P. Shaeffer, Everett Basham, Christopher D. Price
  • Patent number: 6664482
    Abstract: A method of fabricating a zero signal degradation solder bridge electrical connection for connecting adjacent conducting pads of a printed circuit board, and a printed circuit board having at least one of these solder bridge electrical connections. In the method, a stencil, having an opening that corresponds to the adjacent conducting pads and at least a portion of the surface area of the printed circuit board between the adjacent conducting pads, is placed on the surface of printed circuit board. Solder paste is then applied to the stencil such that the solder paste flows through the stencil opening and onto the adjacent conducting pads and at least a portion of the surface area of the printed circuit board between the pads. The stencil is then removed and the printed circuit board is subjected to reflow soldering, thereby fabricating a printed circuit board having a solder bridge electrical connector between adjacent conducting pads.
    Type: Grant
    Filed: May 1, 2000
    Date of Patent: December 16, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Ian P. Shaeffer, Everett Basham, Christopher D. Price
  • Patent number: 6587965
    Abstract: The present invention provides for a method and system for external observation of a dual mode control interface, via a single point of entry/exit from a chip. In operation, data is sent into and retrieved from a chip using a single point on the chip. Multiple test methods can be used with the proper test method selected by an established hierarchy of methods. In one embodiment, an impedance is shown for control purposes between test methods.
    Type: Grant
    Filed: April 29, 2000
    Date of Patent: July 1, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Ian P. Shaeffer, Jeffrey C. Swanson
  • Publication number: 20030014728
    Abstract: A system and method is described for providing a robust mechanical and electrical connection between two or more circuit boards which may be employed for diagnostic purposes and/or for permanent connections. A spacer block, connection block, or pedestal, preferably made of PCB type material is preferably disposed between two PCBs. The pedestal is preferably dimensioned to space the two PCBs far enough apart that the surface mount components on two boards connected employing the inventive pedestal do not interfere with one another. The pedestal preferably provides for ample signal density and signal quality because of the block thickness and availability of insulation within the pedestal.
    Type: Application
    Filed: September 13, 2002
    Publication date: January 16, 2003
    Inventors: Ian P. Shaeffer, Everett Basham
  • Patent number: 6460170
    Abstract: A system and method is described for providing a robust mechanical and electrical connection between two or more circuit boards which may be employed for diagnostic purposes and/or for permanent connections. A spacer block, connection block, or pedestal, preferably made of PCB type material is preferably disposed between two PCBs. The pedestal is preferably dimensioned to space the two PCBs far enough apart that the surface mount components on two boards connected employing the inventive pedestal do not interfere with one another. The pedestal preferably provides for ample signal density and signal quality because of the block thickness and availability of insulation within the pedestal.
    Type: Grant
    Filed: April 29, 2000
    Date of Patent: October 1, 2002
    Assignee: Hewlett Packard Company
    Inventors: Ian P. Shaeffer, Everett Basham