Patents by Inventor Ian P. Shaeffer

Ian P. Shaeffer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9306567
    Abstract: An identifier value stored within a programmable register of a memory device is compared with a selector address received, together with a memory access command, via a signaling interface having at least one I/O node coupled to a bidirectional signaling line. On-die termination circuitry is transitioned between first and second states or maintained in one or the other of the first and second states based, at least in part, on whether the selector address matches the identifier value, with transition to the first state including switchably coupling a first termination resistance between the I/O node and a supply voltage line.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: April 5, 2016
    Assignee: Rambus Inc.
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Patent number: 9257163
    Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: February 9, 2016
    Assignee: RAMBUS INC.
    Inventors: Bret Stott, Frederick A. Ware, Ian P. Shaeffer, Yuanlong Wang
  • Publication number: 20160012869
    Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
    Type: Application
    Filed: September 23, 2015
    Publication date: January 14, 2016
    Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
  • Publication number: 20160005489
    Abstract: An IC die transmits command signals, address signals and data signals to a flash memory device at respective times via a time-multiplexed external signaling line, the data signals representing data to be stored within an array of non-volatile storage elements of the flash memory device. The IC die additionally transmits a control signal to the flash memory device via one or more external control signal lines, the control signal directing the flash memory device to switchably couple an on-die termination element to the time-multiplexed signaling line.
    Type: Application
    Filed: September 17, 2015
    Publication date: January 7, 2016
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Patent number: 9225328
    Abstract: In a non-volatile memory device having an array of non-volatile storage elements, command, address and data signals are received at respective times via a time-multiplexed external signaling line, the data signals representing data to be stored within the array of non-volatile storage elements. A control signal is received via a signaling path external to the non-volatile memory device, and an on-die termination element is switchably coupled to the time-multiplexed signaling line at least in part in response to a transition of the control signal from a first logic state to a second logic state.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: December 29, 2015
    Assignee: Rambus Inc.
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Patent number: 9218243
    Abstract: A memory system supporting error detection and correction (EDC) coverage. The system includes a memory controller and a memory buffer. The memory buffer includes an interface to a first group of memory devices and an interface to a second group of memory devices. The memory buffer accesses data from the first group of memory devices and accesses first error information corresponding to the data from the second group of devices. The memory buffer also accesses additional data from the second group of memory devices and accesses second error information corresponding to the additional data from a device in the first group of memory devices. EDC coverage may also be configured by the memory controller so that some data accesses have EDC coverage and other data accesses do not have EDC coverage.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: December 22, 2015
    Assignee: Rambus Inc.
    Inventor: Ian P. Shaeffer
  • Patent number: 9201444
    Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: December 1, 2015
    Assignee: RAMBUS INC.
    Inventors: Jared L. Zerbe, Ian P. Shaeffer, John Eble
  • Patent number: 9165617
    Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: October 20, 2015
    Assignee: Rambus Inc.
    Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
  • Patent number: 9166583
    Abstract: In a memory module having an integrated-circuit buffer device coupled to one or more integrated-circuit memory devices, the buffer device receives write data signals from an external control component via a set of data inputs, the write data signals indicating write data to be stored within one or more of the memory devices. Logic within the buffer device sequentially applies controllable termination impedance configurations at the data inputs based on an indication received from the control component and an internal state of the buffer device, applying a first controllable termination impedance configuration at each of the data inputs during a first internal state of the buffer device corresponding to the reception of the write data signals on the data inputs, and applying a second controllable termination impedance configuration at each of the data inputs during a second internal state of the buffer device that succeeds the first internal state.
    Type: Grant
    Filed: October 26, 2014
    Date of Patent: October 20, 2015
    Assignee: Rambus Inc.
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Publication number: 20150263733
    Abstract: A memory controller transmits a plurality of control values to a non-volatile memory device together with one or more programming commands. The plurality of control values include (i) a first control value that specifies a first termination resistance to be applied to an I/O node of the non-volatile memory device during an interval in which a first data signal transmitted on a bidirectional signaling line coupled to the I/O node is to be received within the non-volatile memory device and (ii) a second control value that specifies a second termination resistance to be applied to the I/O node during an interval in which a second data signal is transmitted on the bidirectional signaling line by another non-volatile memory device.
    Type: Application
    Filed: June 2, 2015
    Publication date: September 17, 2015
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Patent number: 9135206
    Abstract: An integrated circuit device transmits to a dynamic random access memory (DRAM) one or more commands that specify programming of a digital control value within the DRAM, the digital control value indicating a termination impedance that the DRAM is to couple to a data interface of the DRAM in response to receiving a write command and during reception of write data corresponding to the write command, and that the DRAM is to decouple from the data interface after reception of the write data corresponding to the write command. Thereafter, the integrated circuit device transmits to the DRAM a write command indicating that write data is to be sampled by a data interface of the DRAM during a first time interval and that cause the DRAM to couple the termination impedance to the data interface during the first time interval and decouple the termination impedance from the data interface after the first time interval.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: September 15, 2015
    Assignee: Rambus Inc.
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Publication number: 20150249451
    Abstract: An identifier value stored within a programmable register of a memory device is compared with a selector address received, together with a memory access command, via a signaling interface having at least one I/O node coupled to a bidirectional signaling line. On-die termination circuitry is transitioned between first and second states or maintained in one or the other of the first and second states based, at least in part, on whether the selector address matches the identifier value, with transition to the first state including switchably coupling a first termination resistance between the I/O node and a supply voltage line.
    Type: Application
    Filed: May 14, 2015
    Publication date: September 3, 2015
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Publication number: 20150244364
    Abstract: A non-volatile memory device determines, based at least partly on a first multi-bit device address received via a signaling interface and an incoming chip-select signal, whether the device is to participate in a memory access transaction by receiving or outputting data via an I/O node of the signaling interface. Based at least in part on that determination, on-die termination circuitry within the non-volatile memory device switchably couples or decouples a termination resistance between the I/O node and a supply voltage node during a data transmission phase of the memory access transaction.
    Type: Application
    Filed: May 13, 2015
    Publication date: August 27, 2015
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Publication number: 20150244365
    Abstract: On-die termination circuitry within a non-volatile memory device applies a first termination resistance to an I/O node in response to a data storage command indicating that a data signal conveyed on a bidirectional signaling line is to be received within the non-volatile memory device via the I/O node, and applies a second termination resistance to the I/O node in response to information indicating that another memory device is to output a data signal onto the bidirectional signaling line.
    Type: Application
    Filed: May 13, 2015
    Publication date: August 27, 2015
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Publication number: 20150236694
    Abstract: In a non-volatile memory device having an array of non-volatile storage elements, command, address and data signals are received at respective times via a time-multiplexed external signaling line, the data signals representing data to be stored within the array of non-volatile storage elements. A control signal is received via a signaling path external to the non-volatile memory device, and an on-die termination element is switchably coupled to the time-multiplexed signaling line at least in part in response to a transition of the control signal from a first logic state to a second logic state.
    Type: Application
    Filed: April 24, 2015
    Publication date: August 20, 2015
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Publication number: 20150234707
    Abstract: A dynamic random access memory (DRAM) array is configured for selective repair and error correction of a subset of the array. Error-correcting code (ECC) is provided to a selected subset of the array to protect a row or partial row of memory cells where one or more weak memory cells are detected. By adding a sense amplifier stripe to the edge of the memory array, the adjacent edge segment of the array is employed to store ECC information associated with the protected subsets of the array. Bit replacement is also applied to defective memory cells. By implementing ECC selectively rather than to the entire array, integrity of the memory array is maintained at minimal cost to the array in terms of area and energy consumption.
    Type: Application
    Filed: April 21, 2015
    Publication date: August 20, 2015
    Inventors: Thomas Vogelsang, Suresh N. Rajan, Ian P. Shaeffer, Frederick A. Ware, Wayne F. Ellis
  • Publication number: 20150229306
    Abstract: In a non-volatile memory device having an array of non-volatile storage elements, control information received via one or more control input nodes indicates, at different times, that (i) data signals representative of data to be stored within the array of non-volatile storage elements are to be received via a plurality of input/output (I/O) nodes of the non-volatile memory device, and (ii) data signals representative of data read from the array of non-volatile storage elements are to be output via the plurality of I/O nodes. First termination elements are switchably coupled to and decoupled from the I/O nodes based at least in part on the control information, and second termination elements are switchably coupled to and decoupled from the one or more control input nodes based at least in part on the control information.
    Type: Application
    Filed: April 24, 2015
    Publication date: August 13, 2015
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Patent number: 9104646
    Abstract: Components of a memory system, such as a memory controller and memory device, which detect accumulated memory read disturbances and correct such disturbances before they reach a level that causes errors. The memory device includes a memory array and a disturbance control circuit. The memory array includes a plurality of memory rows. Each memory row is associated with a disturbance warning circuit having a state that corresponds to an accumulated disturbance in the memory row. The disturbance control circuit determines, responsive to an activation of a memory row of the plurality of memory rows specified by a row access command, whether the disturbance condition is present in the memory row based on the state of the disturbance warning circuit associated with the memory row. If a disturbance condition is present, the disturbance control circuit causes a recovery operation to be performed on the memory row to reduce the accumulated disturbances.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: August 11, 2015
    Assignee: Rambus Inc.
    Inventors: Hongzhong Zheng, Brent Haukness, Mehmet Günhan Ertosun, Ian P. Shaeffer
  • Patent number: 9037949
    Abstract: A dynamic random access memory (DRAM) array is configured for selective repair and error correction of a subset of the array. Error-correcting code (ECC) is provided to a selected subset of the array to protect a row or partial row of memory cells where one or more weak memory cells are detected. By adding a sense amplifier stripe to the edge of the memory array, the adjacent edge segment of the array is employed to store ECC information associated with the protected subsets of the array. Bit replacement is also applied to defective memory cells. By implementing ECC selectively rather than to the entire array, integrity of the memory array is maintained at minimal cost to the array in terms of area and energy consumption.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: May 19, 2015
    Assignee: Rambus Inc.
    Inventors: Thomas Vogelsang, Suresh N. Rajan, Ian P. Shaeffer, Frederick A. Ware, Wayne F. Ellis
  • Publication number: 20150134868
    Abstract: Exemplary embodiments include a socket interposer having a plurality of connectors configured to attach to a server board, the server board including: a first processor socket having a processor form factor, and a first memory associated with the first processor socket, a processor inserted into the at least first processor socket, the processor having access to the first memory, and a second processor socket having the processor form factor, and a second memory associated with the second processor socket, wherein the plurality of connectors are configured to fit the processor form factor; and a multi-modal I/O interface having a first mode and a second mode, wherein in the first mode provides processor-to-processor communication, and the second mode provides the first processor with accessibility to the second memory associated with the second processor socket.
    Type: Application
    Filed: August 7, 2014
    Publication date: May 14, 2015
    Inventors: Ian P. Shaeffer, Zhan Ping