Patents by Inventor Ichio Yudasaka

Ichio Yudasaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7067337
    Abstract: Any one of an insulating film forming a TFT, a silicon film and a conductive film is formed by applying a solution and annealing it. In a spin coater (102), a coating solution containing a thin film component which is supplied from a solution storage section (105) is spin-coated onto a substrate. The substrate after coating the coating solution is annealed in an annealing section (103) to form a coating film on the substrate. Additional laser annealing improves one of film characteristics, i.e., crystallinity, density and adhesiveness. Application of the coating solution or a resist by an ink jet process increases utilization of the solution and permits forming a patterned coating film. Because a thin film device in accordance with the present invention is inexpensive and has a high throughput, TFT production by a production system having high utilization of the coating solution drastically reduces initial investment and production cost of a liquid crystal display device.
    Type: Grant
    Filed: July 9, 2002
    Date of Patent: June 27, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Ichio Yudasaka, Tatsuya Shimoda, Sadao Kanbe, Wakao Miyazawa
  • Patent number: 7026236
    Abstract: Method of forming a multilayer interconnection structure of the invention that is a method of forming a multilayer interconnection structure in which a first conductive layer and a second conductive layer are stacked via an insulating layer, and the first conductive layer and the second conductive layer are connected via through holes formed in the insulating layer. The method includes the steps of forming a first conductive layer on a substrate, forming the insulating layer with the through holes on the first conductive layer, filling conductive material into the through holes using a droplet discharge device to form a contact conductive material, and forming the second conductive layer such that it is connected to the contact conductive material.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: April 11, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Hideki Tanaka, Ichio Yudasaka, Mitsuru Sato
  • Patent number: 7015503
    Abstract: Display devices such as EL elements or LED elements, or color filters, are provided, wherewith, when forming thin films such as organic semiconductor films or colored resins, there is remarkably little variation in film thickness from pixel to pixel. A method for fabricating thin film elements having banks of a prescribed height and a thin film layer formed by an ink jet method in areas to be coated that are partitioned by those banks is disclosed. Furthermore, banks are formed of an organic material on a bank formation surface configured of an inorganic material, plasma treatment is performed under conditions that the induction gas is fluorine-based and that fluorine is present excessively, and the areas enclosed by the banks subjected to surface treatment are filled with the liquid thin film material to form the thin film layer or layers.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: March 21, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Shunichi Seki, Hiroshi Kiguchi, Ichio Yudasaka, Hiroo Miyajima
  • Publication number: 20060008956
    Abstract: A method for manufacturing a thin film transistor results in a thin film transistor including a semiconductor film, a channel region provided in the semiconductor film, source and drain regions sandwiching the channel region, and a gate electrode facing the channel region with an intermediary of a gate insulating film. The method includes depositing a droplet that includes a semiconductor material on a substrate; and forming the semiconductor film by drying the droplet to precipitate the semiconductor material on at least a peripheral edge of the droplet.
    Type: Application
    Filed: July 7, 2005
    Publication date: January 12, 2006
    Applicant: Seiko Epson Corporation
    Inventors: Ichio Yudasaka, Takashi Masuda
  • Patent number: 6967352
    Abstract: A thin film formation method in accordance with the present invention forms banks (110) where affinity bank layers and non-affinity bank layers are alternately layered by repeating a step of forming an affinity bank layer (111-11n) with a material having affinity for a thin film material solution (130) (such inorganic material as SiO2) and a step of forming a non-affinity bank layer (121-12n) with a material having non-affinity for the thin film material solution (130) (such organic material as resist) one or more times. Finally the thin film material solution (130) is filled between banks by an ink jet method, heat treatment is executed, and a thin film layer (131-13n) is sequentially layered. By these steps, cost required for affinity control can be decreased and forming multi-layer thin films with uniform film thickness becomes possible.
    Type: Grant
    Filed: April 23, 2004
    Date of Patent: November 22, 2005
    Assignee: Seiko Epson Corporation
    Inventor: Ichio Yudasaka
  • Publication number: 20050196910
    Abstract: Exemplary embodiments of the present invention provide a method of manufacturing a semiconductor device that can take a connection between layers without giving damage to a layer, which is underlying. The semiconductor device includes forming conductive members Ms and Md at a predetermined position of a semiconductor film, forming an insulating film on a whole surface of a substrate excluding the conductive members Ms and Md, and forming a conductive film that is connected to the semiconductor film with the conductive member Ms and Md.
    Type: Application
    Filed: February 24, 2005
    Publication date: September 8, 2005
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Ichio Yudasaka, Hideki Tanaka
  • Publication number: 20050186403
    Abstract: Display devices such as EL elements or LED elements, are formed from thin film elements having banks of prescribed height and a thin film layer formed by an ink jet method in areas to be coated that are partitioned by those banks. The banks may be formed of an organic material on a bank formation surface configured of an inorganic material, plasma treatment is performed under conditions that the induction gas is fluorine-based and that fluorine is present excessively, and the areas enclosed by the banks subjected to surface treatment are filled with the liquid thin film material to form the thin film layer or layers.
    Type: Application
    Filed: March 31, 2005
    Publication date: August 25, 2005
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Shunichi Seki, Hiroshi Kiguchi, Ichio Yudasaka, Hiroo Miyajima
  • Publication number: 20050184293
    Abstract: Exemplary embodiments of the present invention are intended to provide a semiconductor device that can readily address or achieve high integration. Exemplary embodiments provide a semiconductor device constructed to include a transistor and a multi-layer wiring structure electrically connected to the transistor, the multi-layer wiring structure having a first wiring layer disposed in the same layer as the semiconductor layer of the transistor.
    Type: Application
    Filed: February 22, 2005
    Publication date: August 25, 2005
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Ichio Yudasaka
  • Patent number: 6933571
    Abstract: In a TFT including on the surface side of a substrate a channel region opposed to a gate electrode, with a gate insulating film provided therebetween, and a source-drain region connected to the channel region, and a TFT including a source-drain wiring layer electrically connected to the source-drain region, and a gate wiring layer electrically connected to the gate electrode, at least one component part composed of a conductive film or a semiconductor film, among the component parts of each TFT, is provided with a heat-radiating extension extended from the component part itself for enhancing the heat-radiating efficiency from the component part.
    Type: Grant
    Filed: January 15, 2004
    Date of Patent: August 23, 2005
    Assignee: Seiko Epson Corporation
    Inventors: Satoshi Inoue, Ichio Yudasaka
  • Publication number: 20050170096
    Abstract: In order to provide an active matrix display device in which a thick insulating film is preferably formed around an organic semiconductive film of a thin film luminescent device without damaging the thin film luminescent device, the active matrix display device is provided with a bank layer (bank) along a data line (sig) and a scanning line (gate) to suppress formation of parasitic capacitance in the data line (sig), in which the bank layer (bank) surrounds a region that forms the organic semiconductive film of the thin film luminescent device by an ink-jet process. The bank layer (bank) includes a lower insulating layer formed of a thick organic material and an upper insulating layer of an organic material which is deposited on the lower insulating layer and has a smaller thickness so as to avoid contact of the organic semiconductive film with the upper insulating layer.
    Type: Application
    Filed: March 4, 2005
    Publication date: August 4, 2005
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Ichio Yudasaka
  • Publication number: 20050170076
    Abstract: Display devices such as EL elements or LED elements, are formed from thin film elements having banks of prescribed height and a thin film layer formed by an ink jet method in areas to be coated that are partitioned by those banks. The banks may be formed of an organic material on a bank formation surface configured of an inorganic material, plasma treatment is performed under conditions that the induction gas is fluorine-based and that fluorine is present excessively, and the areas enclosed by the banks subjected to surface treatment are filled with the liquid thin film material to form the thin film layer or layers.
    Type: Application
    Filed: March 31, 2005
    Publication date: August 4, 2005
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Shunichi Seki, Hiroshi Kiguchi, Ichio Yudasaka, Hiroo Miyajima
  • Publication number: 20050170550
    Abstract: Display devices such as EL elements or LED elements, are formed from thin film elements having banks of prescribed height and a thin film layer formed by an ink jet method in areas to be coated that are partitioned by those banks. The banks may be formed of an organic material on a bank formation surface configured of an inorganic material, plasma treatment is performed under conditions that the induction gas is fluorine-based and that fluorine is present excessively, and the areas enclosed by the banks subjected to surface treatment are filled with the liquid thin film material to form the thin film layer or layers.
    Type: Application
    Filed: March 31, 2005
    Publication date: August 4, 2005
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Shunichi Seki, Hiroshi Kiguchi, Ichio Yudasaka, Hiroo Miyajima
  • Publication number: 20050161836
    Abstract: Aspects of the invention can provide an alignment method that is preferably applicable when manufacturing equipments by liquid-phase processing. The alignment method in a device manufacturing process can include forming of a functional film on a substrate by liquid-phase processing, forming an alignment mark on the substrate on which the functional film is formed so as to make a pattern of the alignment mark appear on a film that is formed after forming the functional film, and aligning the film that is formed after forming the functional film by using the alignment mark.
    Type: Application
    Filed: December 21, 2004
    Publication date: July 28, 2005
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Ichio Yudasaka, Hideki Tanaka
  • Publication number: 20050157222
    Abstract: A simple method of manufacturing a semiconductor device including a thick and dense insulator layer having a uniform film thickness includes forming the insulator layer by repeatedly applying a liquid material to a conductive layer plural times.
    Type: Application
    Filed: January 11, 2005
    Publication date: July 21, 2005
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Hideki Tanaka, Ichio Yudasaka, Masami Miyasaka
  • Patent number: 6884700
    Abstract: A method of manufacturing a device comprising individual thin films including a silicon film, a gate insulating film, a conductive film for a gate electrode, an interlayer insulating film, and a conductive film for an electrode and wiring, comprising: a step of applying a liquid material to form an applied film; and a heat treatment and/or a light irradiating treatment of making the applied film into the silicon film, wherein, as the liquid material, a high-order silane composition comprising a high-order silence formed by photopolymerization by irradiating a silane compound solution having a photopolymerization property with UV rays is used.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: April 26, 2005
    Assignee: Seiko Epson Corporation
    Inventors: Takashi Aoki, Masahiro Furusawa, Ichio Yudasaka
  • Patent number: 6885148
    Abstract: In order to provide an active matrix display device in which a thick insulating film is preferably formed around an organic semiconductive film of a thin film luminescent device without damaging the thin film luminescent device, the active matrix display device is provided with a bank layer (bank) along a data line (sig) and a scanning line (gate) to suppress formation of parasitic capacitance in the data line (sig), in which the bank layer (bank) surrounds a region that forms the organic semiconductive film of the thin film luminescent device by an ink-jet process. The bank layer (bank) includes a lower insulating layer formed of a thick organic material and an upper insulating layer of an organic material which is deposited on the lower insulating layer and has a smaller thickness so as to avoid contact of the organic semiconductive film with the upper insulating layer.
    Type: Grant
    Filed: July 11, 2003
    Date of Patent: April 26, 2005
    Assignee: Seiko Epson Corporation
    Inventor: Ichio Yudasaka
  • Patent number: 6881501
    Abstract: The invention increases the outgoing efficiency of light generated in an organic luminous layer of an organic electroluminescence element without decreasing the numerical aperture. A light-transmissive anode electrode layer, an organic luminous layer, and a light-reflective cathode layer are provided on the entire surface of one pixel region. On the anode layer, the organic luminous layer, and the cathode layer, slopes are installed protruding from the anode layer side to the cathode layer side. By this, light generated in the organic luminous layer, and irradiated in parallel to a cumulate surface of a cumulate body, is reflected by the slope on the boundary between the organic luminous layer and the cathode layer and exits toward the anode layer side.
    Type: Grant
    Filed: March 12, 2001
    Date of Patent: April 19, 2005
    Assignee: Seiko Epson Corporation
    Inventor: Ichio Yudasaka
  • Patent number: 6864133
    Abstract: A device comprising a semiconductor film (12) formed on a substrate (11), a gate region (15), in which a gate insulating film (13) formed on the semiconductor film and a gate electrode film (14) are laminated, isolation means (A) formed on both sides of the gate region to prevent contact between the gate electrode film and other regions, and a source region and a drain region formed by baking a liquid semiconductor material (17) and disposed on regions on the substrate and on both sides of the gate region.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: March 8, 2005
    Assignee: Seiko Epson Corporation
    Inventors: Takashi Aoki, Masahiro Furusawa, Ichio Yudasaka
  • Publication number: 20050029591
    Abstract: There is provided a transistor and a method of manufacturing this transistor that allow a high degree of freedom when designing a wiring structure and also allow an improvement in product quality to be achieved. The transistor includes a source area, a drain area, and a channel area, each of which are formed by semiconductor films, and also a gate insulating film and a gate electrode. The semiconductor film containing the source area and the semiconductor film containing the drain area are formed separately sandwiching both sides of an insulating member. The semiconductor film containing the channel area is formed on top of the insulating member.
    Type: Application
    Filed: November 21, 2003
    Publication date: February 10, 2005
    Applicant: Seiko Epson Corporation
    Inventors: Ichio Yudasaka, Masahiro Furusawa, Takashi Aoki
  • Publication number: 20050026421
    Abstract: Method of forming a multilayer interconnection structure of the invention that is a method of forming a multilayer interconnection structure in which a first conductive layer and a second conductive layer are stacked via an insulating layer, and the first conductive layer and the second conductive layer are connected via through holes formed in the insulating layer. The method includes the steps of forming a first conductive layer on a substrate, forming the insulating layer with the through holes on the first conductive layer, filling conductive material into the through holes using a droplet discharge device to form a contact conductive material, and forming the second conductive layer such that it is connected to the contact conductive material.
    Type: Application
    Filed: June 29, 2004
    Publication date: February 3, 2005
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Hideki Tanaka, Ichio Yudasaka, Mitsuru Sato