Patents by Inventor In-Lung Chu

In-Lung Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10566294
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, at least one semiconductor device, a through-substrate via (TSV), and a shield structure. The substrate has a front side surface and a back side surface. The semiconductor device is disposed on the front side surface. The TSV is disposed in the substrate. The TSV is exposed by the front side surface and the back side surface, and the TSV is electrically connected to the semiconductor device. The shield structure is disposed in the substrate and surrounds the TSV. The shield structure is exposed by the front side surface, the shield structure is electrically isolated from the TSV, and the shield structure and the TSV have bottom ends at the same height.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: February 18, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Po-Chun Lin, Chin-Lung Chu
  • Patent number: 10446514
    Abstract: A manufacturing method of a combing bump structure is disclosed. In the manufacturing method, a semiconductor substrate is provided, a pad is formed on the semiconductor substrate, a conductive layer is formed on the pad, a solder bump is formed on the conductive layer, and at least two metal side walls are formed disposed along opposing laterals of the solder bump respectively.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: October 15, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Po-Chun Lin, Chin-Lung Chu
  • Publication number: 20190281716
    Abstract: A casing of an electronic device including a metallic housing and a first non-conductive spacer is provided. The metallic housing has an inner surface and an outer surface opposite to the inner surface, and the outer surface has a back side and lateral sides connecting with the back side. The inner surface is substantially a recessed structure. The metallic housing has a first gap communicating the inner surface and the outer surface, and the metallic housing further includes a second gap and at least one connecting terminal. The first non-conductive spacer is selectively disposed in the first gap of the metallic housing, and extends from a first side of the lateral sides of the metallic housing to the back side of the metallic housing.
    Type: Application
    Filed: May 29, 2019
    Publication date: September 12, 2019
    Applicant: HTC Corporation
    Inventors: Tim Chung-Ting Wu, Cheng-Chieh Chuang, Chi-Jen Lu, Chun-Lung Chu, Chien-Hung Lin
  • Patent number: 10373932
    Abstract: A stacked semiconductor structure is provided. The stacked semiconductor structure includes a substrate, a first electronic component, a first fillet, and a first redistribution layer. The substrate has a support surface. The substrate includes a first pad disposed on the support surface. The first electronic component is disposed on the support surface and has a first bottom surface, a first top surface, and a first side surface connecting the first bottom surface and the first top surface. The first electronic component includes a second pad disposed on the first top surface. The first fillet is disposed on the support surface and the first side surface and has a first inclined surface. The first redistribution layer is disposed on the support surface, the first top surface, and the first inclined surface and electrically connecting the first pad to the second pad.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: August 6, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Po-Chun Lin, Chin-Lung Chu
  • Patent number: 10356923
    Abstract: A casing of an electronic device including a metallic housing and a first non-conductive spacer is provided. The metallic housing has an inner surface and an outer surface opposite to the inner surface, the outer surface of the metallic housing is dyed, the inner surface is substantially a recessed structure, and the metallic housing has a first gap communicating the inner surface and the outer surface, wherein the metallic housing further comprises at least one connecting terminal. The first non-conductive spacer, disposed in the first gap of the metallic housing.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: July 16, 2019
    Assignee: HTC Corporation
    Inventors: Tim Chung-Ting Wu, Cheng-Chieh Chuang, Chi-Jen Lu, Chun-Lung Chu, Chien-Hung Lin
  • Patent number: 10290512
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate and a first conductive bump. The semiconductor substrate has an integrated circuit and an interconnection metal layer, and a tilt surface is formed on an edge of the semiconductor substrate. The first conductive bump is electrically connected to the integrated circuit via the interconnection metal layer, and is disposed on the tilt surface, wherein a profile of the first conductive bump extends beyond a side surface of the edge of the semiconductor layer.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: May 14, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Po-Chun Lin, Chin-Lung Chu
  • Publication number: 20190122996
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, at least one semiconductor device, a through-substrate via (TSV), and a shield structure. The substrate has a front side surface and a back side surface. The semiconductor device is disposed on the front side surface. The TSV is disposed in the substrate. The TSV is exposed by the front side surface and the back side surface, and the TSV is electrically connected to the semiconductor device. The shield structure is disposed in the substrate and surrounds the TSV. The shield structure is exposed by the front side surface, the shield structure is electrically isolated from the TSV, and the shield structure and the TSV have bottom ends at the same height.
    Type: Application
    Filed: November 28, 2018
    Publication date: April 25, 2019
    Inventors: Po-Chun LIN, Chin-Lung CHU
  • Publication number: 20190109113
    Abstract: The present disclosure is directed to a method for preparing a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique and a method for preparing the same. The method includes the steps of forming a first semiconductor device having a first conductive portion, a first dielectric portion adjacent to the first conductive portion, and a depression at an upper surface of the first conductive portion; forming a second semiconductor device having a second conductive portion and a second dielectric portion adjacent to the second conductive portion; disposing the first semiconductor device and the second semiconductor device in a manner such that the first conductive portion faces the second conductive portion; and expanding at least one of the first conductive portion and the second conductive portion to fill the depression.
    Type: Application
    Filed: December 4, 2018
    Publication date: April 11, 2019
    Inventors: Po-Chun LIN, Chin-Lung CHU
  • Patent number: 10250980
    Abstract: A digital microphone is provided. The digital microphone includes an acoustic sensor, a bias generator, first and second attenuators, a buffer, an amplifier, an ADC, and a controller. The acoustic sensor transfers an acoustic signal to a voltage signal. The bias generator provides a bias voltage to the acoustic sensor. The first attenuator attenuates the voltage signal by a first attenuation value. The buffer buffers the voltage signal to generate a buffered voltage signal. The amplifier amplifies the buffered voltage signal to generate an amplified signal. The ADC converts the amplified signal to a data signal with a digital format. The second attenuator attenuates the data signal by a second attenuation value. The controller determines whether the amplified signal is larger than a reference value and adjusts the bias voltage and the first and second attenuation values of the first and second attenuators according to the result determined by the controller.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: April 2, 2019
    Assignee: FORTEMEDIA, INC.
    Inventors: Ion Opris, Abu Hena M Kamal, Lee Tay Chew, Ramesh Prakash, Shomo Chen, Qiang Wei, Lung-Chu Joseph Chen
  • Publication number: 20190074197
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate and a first conductive bump. The semiconductor substrate has an integrated circuit and an interconnection metal layer, and a tilt surface is formed on an edge of the semiconductor substrate. The first conductive bump is electrically connected to the integrated circuit via the interconnection metal layer, and is disposed on the tilt surface, wherein a profile of the first conductive bump extends beyond a side surface of the edge of the semiconductor layer.
    Type: Application
    Filed: November 7, 2018
    Publication date: March 7, 2019
    Inventors: Po-Chun LIN, Chin-Lung CHU
  • Patent number: 10192853
    Abstract: The present disclosure provides a method for preparing a semiconductor apparatus. The semiconductor apparatus includes a first semiconductor die and a second semiconductor die stacked onto the first semiconductor die in a horizontally shifted manner. The first semiconductor die includes a first chip selection terminal and a first lower terminal electrically connected to the first chip selection terminal. The second semiconductor die includes a second chip selection terminal electrically connected to a first upper terminal of the first semiconductor die via a second lower terminal of the second semiconductor die. The first upper terminal which is electrically connected to the second chip selection terminal is not electrically connected to the first lower terminal which is electrically connected to the first chip selection terminal.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: January 29, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Po-Chun Lin, Chin-Lung Chu
  • Patent number: 10170432
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, at least one semiconductor device, a through-substrate via (TSV), and a shield structure. The substrate has a front side surface and a back side surface. The semiconductor device is disposed on the front side surface. The TSV is disposed in the substrate. The TSV is exposed by the front side surface and the back side surface, and the TSV is electrically connected to the semiconductor device. The shield structure is disposed in the substrate and surrounds the TSV. The shield structure is exposed by the front side surface, the shield structure is electrically isolated from the TSV, and the shield structure is used to be electrically connected to a power terminal or a ground terminal.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: January 1, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Po-Chun Lin, Chin-Lung Chu
  • Publication number: 20180374818
    Abstract: The present disclosure is directed to method for preparing a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique. The method includes operations of forming a first semiconductor device having a first conductive portion, a first dielectric portion adjacent to the first conductive portion, and a depression at an upper surface of the first conductive portion; forming a second semiconductor device having a second conductive portion and a second dielectric portion adjacent to the second conductive portion; disposing the first semiconductor device and the second semiconductor device in a manner such that the first conductive portion faces the second conductive portion; and expanding at least one of the first conductive portion and the second conductive portion to fill the depression.
    Type: Application
    Filed: August 31, 2018
    Publication date: December 27, 2018
    Inventors: PO-CHUN LIN, CHIN-LUNG CHU
  • Publication number: 20180337154
    Abstract: A manufacturing method of a combing bump structure is disclosed. In the manufacturing method, a semiconductor substrate is provided, a pad is formed on the semiconductor substrate, a conductive layer is formed on the pad, a solder bump is formed on the conductive layer, and at least two metal side walls are formed disposed along opposing laterals of the solder bump respectively.
    Type: Application
    Filed: July 30, 2018
    Publication date: November 22, 2018
    Inventors: Po-Chun LIN, Chin-Lung CHU
  • Publication number: 20180337116
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate and a first conductive bump. The semiconductor substrate has an integrated circuit and an interconnection metal layer, and a tilt surface is formed on an edge of the semiconductor substrate. The first conductive bump is electrically connected to the integrated circuit via the interconnection metal layer, and is disposed on the tilt surface, wherein a profile of the first conductive bump extends beyond a side surface of the edge of the semiconductor layer.
    Type: Application
    Filed: May 17, 2017
    Publication date: November 22, 2018
    Inventors: Po-Chun LIN, Chin-Lung CHU
  • Publication number: 20180315725
    Abstract: A package structure includes a semiconductor substrate: a pad disposed on the semiconductor substrate; a conductive layer disposed on the pad; a protection coating; and a metal bump disposed on the conductive layer, and the metal bump covered with the protection coating so as to avoid oxidation of the metal bump.
    Type: Application
    Filed: April 26, 2017
    Publication date: November 1, 2018
    Inventors: Po-Chun LIN, Chin-Lung CHU
  • Publication number: 20180308803
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, at least one semiconductor device, a through-substrate via (TSV), and a shield structure. The substrate has a front side surface and a back side surface. The semiconductor device is disposed on the front side surface. The TSV is disposed in the substrate. The TSV is exposed by the front side surface and the back side surface, and the TSV is electrically connected to the semiconductor device. The shield structure is disposed in the substrate and surrounds the TSV. The shield structure is exposed by the front side surface, the shield structure is electrically isolated from the TSV, and the shield structure is used to be electrically connected to a power terminal or a ground terminal.
    Type: Application
    Filed: April 20, 2017
    Publication date: October 25, 2018
    Inventors: Po-Chun LIN, Chin-Lung CHU
  • Publication number: 20180308823
    Abstract: A stacked semiconductor structure is provided. The stacked semiconductor structure includes a substrate, a first electronic component, a first fillet, and a first redistribution layer. The substrate has a support surface. The substrate includes a first pad disposed on the support surface. The first electronic component is disposed on the support surface and has a first bottom surface, a first top surface, and a first side surface connecting the first bottom surface and the first top surface. The first electronic component includes a second pad disposed on the first top surface. The first fillet is disposed on the support surface and the first side surface and has a first inclined surface. The first redistribution layer is disposed on the support surface, the first top surface, and the first inclined surface and electrically connecting the first pad to the second pad.
    Type: Application
    Filed: April 20, 2017
    Publication date: October 25, 2018
    Inventors: Po-Chun LIN, Chin-Lung CHU
  • Patent number: 10104472
    Abstract: An acoustic capture device includes an acoustic transducer, an acoustic detector, an analog-to-digital converter, and a processing element. The acoustic transducer captures an acoustic wave to generate an analog signal. The acoustic detector detects, according to the analog signal, a specific event to generate a trigger signal. The analog-to-digital converter converts the analog signal to generate a digital signal. The processing element receives the trigger signal to execute a control process. The control process includes: analyzing the digital signal to determine ambient information; determining a first set of parameters of the acoustic detector according to the ambient information; performing a control information protocol to adjust the acoustic detector according to the first set of parameters; and performing, according to the ambient information, an enhancement processing on the digital signal to generate an enhanced digital signal.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: October 16, 2018
    Assignee: FORTEMEDIA, INC.
    Inventors: Qiang Wei, Lung-Chu Joseph Chen, Powen Ru, Qing-Guang Liu, Yen-Son Paul Huang
  • Patent number: 10068865
    Abstract: A combing bump structure includes a semiconductor substrate, a pad, a conductive layer, a solder bump and at least two metal side walls The pad is disposed on the semiconductor substrate. The conductive layer is disposed on the pad. The solder bump is disposed on the conductive layer. The at least two metal side walls are disposed along opposing outer side walls of the solder bump respectively.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: September 4, 2018
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Po-Chun Lin, Chin-Lung Chu