Abstract: The present disclosure is directed to a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique and a method for preparing the same. The semiconductor devices have conductive portions with higher coefficient of thermal expansion than their dielectric portions. By forming the depression to provide a space for the volume expansion of the conductive portion with higher coefficient of thermal expansion during the subsequent thermal treating process of the fusion bonding, the semiconductor apparatus formed of semiconductor devices by the fusion bonding technique does not exhibit a lateral protrusion into the interface between the two dielectric portions. As a result, the failure of the electrical function due to the lateral protrusion is effectively eliminated.

Abstract: A semiconductor structure includes a first die; a second die disposed over or at least partially in contact with the first die; a redistribution layer (RDL) disposed over the second die; a conductive pillar extended between the first die and the RDL; and a molding surrounding the first die, the second die and the conductive pillar, wherein the first die and the RDL are electrically connected by the conductive pillar.

Abstract: A die device includes a die including an active layer; and an interconnect feature configured for electrical connection of the active layer, wherein the interconnect feature is in contact with a substrate in the die; and a bump, independent of the die, configured for electrical connection of the active layer.

Abstract: A semiconductor structure includes a substrate including a conductive pillar protruded from the substrate; and a first chip disposed over the substrate and including a first via extended through the first chip, wherein the conductive pillar is extended from the substrate through the first chip and is partially disposed within the first via.

Abstract: The present disclosure is directed to a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique and a method for preparing the same. The semiconductor devices have conductive portions with higher coefficient of thermal expansion than their dielectric portions. By forming the depression to provide a space for the volume expansion of the conductive portion with higher coefficient of thermal expansion during the subsequent thermal treating process of the fusion bonding, the semiconductor apparatus formed of semiconductor devices by the fusion bonding technique does not exhibit a lateral protrusion into the interface between the two dielectric portions. As a result, the failure of the electrical function due to the lateral protrusion is effectively eliminated.

Abstract: A die device includes a die including an active layer; and an interconnect feature configured for electrical connection of the active layer, wherein the interconnect feature is in contact with a substrate in the die; and a bump, independent of the die, configured for electrical connection of the active layer.

Abstract: The present disclosure provides a method for preparing a semiconductor apparatus. The semiconductor apparatus includes a first semiconductor die and a second semiconductor die stacked onto the first semiconductor die in a horizontally shifted manner. The first semiconductor die includes a first chip selection terminal and a first lower terminal electrically connected to the first chip selection terminal. The second semiconductor die includes a second chip selection terminal electrically connected to a first upper terminal of the first semiconductor die via a second lower terminal of the second semiconductor die. The first upper terminal which is electrically connected to the second chip selection terminal is not electrically connected to the first lower terminal which is electrically connected to the first chip selection terminal.

Abstract: A method for forming an interconnect of a solid oxide fuel cell includes the following steps. First of all, a powder mixture substantially including equal to or more than 90 wt % chromium powder, with the balance being iron powder and inevitable impurities, is provided. Then the powder mixture is pressurized by a pressing process with a pressure equal to or over 8 mt/cm2 to form a green interconnect with a density being equal to or over 90% of the theoretical density. Next the green interconnect is sintered by a sintering process to form an interconnect body. Finally, a protection process is performed on at least one surface of the interconnect body to form an interconnect.

Abstract: The present disclosure provides a method far preparing a semiconductor package. The semiconductor package includes a semiconductor device having an upper surface and a side, wherein the upper surface and the side form a corner of the semiconductor device. The semiconductor package also includes a lateral bump structure disposed on the side and implementing a lateral signal path of the semiconductor device. The semiconductor package further includes a vertical hump structure disposed over the upper surface and implementing a vertical signal path of the semiconductor device.

Abstract: A semiconductor apparatus includes a first semiconductor die and a second semiconductor die stacked onto the first semiconductor die in a horizontally shifted manner. The first semiconductor die includes a first chip selection terminal and a first lower terminal electrically connected to the first chip selection terminal. The second semiconductor die includes a second chip selection terminal electrically connected to a first upper terminal of the first semiconductor die via a second lower terminal of the second semiconductor die. The first upper terminal which is electrically connected to the second chip selection terminal is not electrically connected to the first lower terminal which is electrically connected to the first chip selection terminal.

Abstract: The invention is directed to a droplet actuator device and methods for integrating gel electrophoresis analysis with pre or post-analytical sample handling as well as other molecular analysis processes. Using digital microfluidics technology, the droplet actuator device and methods of the invention provide the ability to perform gel electrophoresis and liquid handling operations on a single integrated device. The integrated liquid handling operations may be used to prepare and deliver samples to the electrophoresis gel, capture and subsequently process products of the electrophoresis gel or perform additional assays on the same sample materials which are analyzed by gel electrophoresis. In one embodiment, one or more molecular assays, such as nucleic acid (e.g., DNA) quantification by real-time PCR, and one or more sample processing operations such as sample dilution is performed on a droplet actuator integrated with an electrophoresis gel.

Abstract: A digital microphone is provided. The digital microphone includes an acoustic sensor, a bias generator, first and second attenuators, a buffer, an amplifier, an ADC, and a controller. The acoustic sensor transfers an acoustic signal to a voltage signal. The bias generator provides a bias voltage to the acoustic sensor. The first attenuator attenuates the voltage signal by a first attenuation value. The buffer buffers the voltage signal to generate a buffered voltage signal. The amplifier amplifies the buffered voltage signal to generate an amplified signal. The ADC converts the amplified signal to a data signal with a digital format. The second attenuator attenuates the data signal by a second attenuation value. The controller determines whether the amplified signal is larger than a reference value and adjusts the bias voltage and the first and second attenuation values of the first and second attenuators according to the result determined by the controller.

Abstract: A semiconductor package includes a semiconductor device having an upper surface and a side, wherein the upper surface and the side form a corner of the semiconductor device. The semiconductor package also includes a lateral bump structure disposed on the side and implementing a lateral signal path of the semiconductor device. The semiconductor package further includes a vertical bump structure disposed over the upper surface and implementing a vertical signal path of the semiconductor device.

Abstract: The present disclosure provides a semiconductor apparatus having a plurality of semiconductor dies stacked in a face-to-face manner and a method for preparing the same. By stacking dies having different functions vertically in a face-to-face manner, a face-to-face communication is implemented between the dies having different functions. In addition, stacking the dies having different functions vertically in a face-to-face manner reduces the occupied area of the semiconductor apparatus, as compared to a semiconductor apparatus with dies having different functions arranged in a laterally adjacent manner. Furthermore, the signal path of the dies having different functions vertically stacked in the face-to-face manner is shorter than the signal path of the dies having different functions arranged in a laterally adjacent manner; consequently, the dies having different functions vertically stacked in the face-to-face manner of the present disclosure can be applied to high-speed electronic devices.

Abstract: A semiconductor chip includes a semiconductor device with an upper surface and a lower surface opposite to the upper surface. The semiconductor device includes an input terminal, a plurality of through silicon vias, a plurality of selection pads, a plurality of tilt pads and a plurality of tilt conductive structures. The through silicon vias are extended through the semiconductor device. The selection pads are located on the lower surface The tilt pads are located on the upper surface and connected to the selection pads through the through silicon vias respectively. Each tilt pad includes a pad surface that is non-parallel to the upper surface. A lower end of each tilt conductive structure is in contact with the pad surface of each tilt pad, and an upper end of each tilt conductive structure is vertically overlapped with an immediately-adjacent one of the tilt pads.

Abstract: A non-volatile memory includes a substrate, a stacked structure, a channel layer, and a second dielectric layer. The stacked structure includes a first dielectric layer and a plurality of memory cells. The first dielectric layer is disposed on the substrate. The memory cells are stacked on the first dielectric layer. Each of the memory cells includes two first conductive layers and a charge storage structure. The charge storage structure is disposed between the two first conductive layers. The charge storage structures in the vertically adjacent memory cells are separated from each other. The channel layer is disposed on a sidewall of the stacked structure and connected to the substrate. The second dielectric layer is disposed between the channel layer and the first conductive layers.

Abstract: An acoustic capture device includes an acoustic transducer, an acoustic detector, an analog-to-digital converter, and a processing element. The acoustic transducer captures an acoustic wave to generate an analog signal. The acoustic detector detects, according to the analog signal, a specific event to generate a trigger signal. The analog-to-digital converter converts the analog signal to generate a digital signal. The processing element receives the trigger signal to execute a control process. The control process includes: analyzing the digital signal to determine ambient information; determining a first set of parameters of the acoustic detector according to the ambient information; performing a control information protocol to adjust the acoustic detector according to the first set of parameters; and performing, according to the ambient information, an enhancement processing on the digital signal to generate an enhanced digital signal.

Abstract: A method for managing periodic packets, a server and a network equipment are provided. The method includes the steps of receiving at least one transmission parameter of a plurality of periodic packets, determining at least one time sequence for rearranging and transmitting the periodic packets according to the at least one transmission parameter, transmitting the at least one time sequence, and receiving and disassembling the periodic packets already rearranged and transmitted according to the at least one time sequence.

Abstract: A method of manufacturing a casing of an electronic device including the following steps is provided. A metallic housing is provided, wherein the metallic housing has an inner surface and an outer surface opposite to the inner surface. A plurality of apertures are formed on the inner surface of the metallic housing. A non-conductive layer is formed on the inner surface of the metallic housing, and part of the non-conductive layer is extended into the apertures. The outer surface of the metallic housing is dyed to form the casing of the electronic device. A casing of an electronic device is also provided.

Abstract: A method for fabricating semiconductor device is disclosed. A substrate having a first gate layer and a first dielectric layer thereon is provided. A shallow trench isolation (STI) is formed in the substrate and surrounds the first gate layer and the first dielectric layer. The first dielectric layer is removed. A first spacer is formed on the sidewall of the STI above the first gate layer. Using the first spacer as mask, part of the first gate layer and part of the substrate are removed for forming a first opening while defining a first gate structure and a second gate structure.