Patents by Inventor Jeehwan Kim

Jeehwan Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Cone-shaped holes for high efficiency thin film solar cells
    Patent number: 10056510
    Abstract: A photovoltaic device includes a substrate having a plurality of hole shapes formed therein. The plurality of hole shapes each have a hole opening extending from a first surface and narrowing with depth into the substrate. The plurality of hole shapes form a hole pattern on the first surface, and the hole pattern includes flat areas separating the hole shapes on the first surface. A photovoltaic device stack is formed on the first surface and extends into the hole shapes. Methods are also provided.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: August 21, 2018
    Assignee: International Business Machines Corporation
    Inventors: Keith E. Fogel, Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana
  • RESONANT CAVITY STRAINED III-V PHOTODETECTOR AND LED ON SILICON SUBSTRATE
    Publication number: 20180226539
    Abstract: An optoelectronic device that includes a germanium containing buffer layer atop a silicon containing substrate, and a first distributed Bragg reflector stack of III-V semiconductor material layers on the buffer layer. The optoelectronic device further includes an active layer of III-V semiconductor material present on the first distributed Bragg reflector stack, wherein a difference in lattice dimension between the active layer and the first distributed brag reflector stack induces a strain in the active layer. A second distributed Bragg reflector stack of III-V semiconductor material layers having a may be present on the active layer.
    Type: Application
    Filed: April 9, 2018
    Publication date: August 9, 2018
    Inventors: Jeehwan Kim, Ning Li, Devendra K. Sadana
  • RESONANT CAVITY STRAINED III-V PHOTODETECTOR AND LED ON SILICON SUBSTRATE
    Publication number: 20180226540
    Abstract: An optoelectronic device that includes a germanium containing buffer layer atop a silicon containing substrate, and a first distributed Bragg reflector stack of III-V semiconductor material layers on the buffer layer. The optoelectronic device further includes an active layer of III-V semiconductor material present on the first distributed Bragg reflector stack, wherein a difference in lattice dimension between the active layer and the first distributed brag reflector stack induces a strain in the active layer. A second distributed Bragg reflector stack of III-V semiconductor material layers having a may be present on the active layer.
    Type: Application
    Filed: April 9, 2018
    Publication date: August 9, 2018
    Inventors: Jeehwan Kim, Ning Li, Devendra K. Sadana
  • Highly responsive III-V photodetectors using ZnO:Al as n-type emitter
    Patent number: 10043920
    Abstract: A photodiode includes a p-type ohmic contact and a p-type substrate in contact with the p-type ohmic contact. An intrinsic layer is formed over the substrate and including a III-V material. A transparent II-VI n-type layer is formed on the intrinsic layer and functions as an emitter and an n-type ohmic contact.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: August 7, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jeehwan Kim, Ning Li, Devendra K. Sadana, Brent A. Wacaser
  • SELECTIVE EPITAXY USING EPITAXY-PREVENTION LAYERS
    Publication number: 20180218900
    Abstract: A method for forming an epitaxial structure includes providing a two-dimensional material on a crystal semiconductor material and opening up portions of the two-dimensional material to expose the crystal semiconductor material. A structure is epitaxially grown in the portions opened up in the crystal semiconductor material such that the epitaxial growth is selective to the exposed crystal semiconductor material relative to the two-dimensional material.
    Type: Application
    Filed: March 26, 2018
    Publication date: August 2, 2018
    Inventors: Cheng-Wei Cheng, Jeehwan Kim, John A. Ott, Devendra K. Sadana
  • Junction interlayer dielectric for reducing leakage current in semiconductor devices
    Patent number: 10038057
    Abstract: A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. A dielectric interlayer is formed on the p-doped layer. An n-type layer is formed on the dielectric interlayer, the n-type layer including a high band gap II-VI material to form an electronic device.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: July 31, 2018
    Assignee: International Business Machines Corporation
    Inventors: Joel P. de Souza, Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana, Brent A. Wacaser
  • SYSTEMS AND METHODS FOR GRAPHENE BASED LAYER TRANSFER
    Publication number: 20180197736
    Abstract: A graphene-based layer transfer (GBLT) technique is disclosed. In this approach, a device layer including a III-V semiconductor, Si, Ge, III-N semiconductor, SiC, SiGe, or II-VI semiconductor is fabricated on a graphene layer, which in turn is disposed on a substrate. The graphene layer or the substrate can be lattice-matched with the device layer to reduce defect in the device layer. The fabricated device layer is then removed from the substrate via, for example, a stressor attached to the device layer. In GBLT, the graphene layer serves as a reusable and universal platform for growing device layers and also serves a release layer that allows fast, precise, and repeatable release at the graphene surface.
    Type: Application
    Filed: March 7, 2018
    Publication date: July 12, 2018
    Inventor: Jeehwan KIM
  • Atomic layer deposition for photovoltaic devices
    Patent number: 10008625
    Abstract: A photovoltaic device and method include a substrate, a conductive layer formed on the substrate and an absorber layer formed on the conductive layer from a Cu—Zn—Sn containing chalcogenide material. An emitter layer is formed on the absorber layer and a buffer layer is formed on the emitter layer including an atomic layer deposition (ALD) layer. A transparent conductor layer is formed on the buffer layer.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: June 26, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jeehwan Kim, David B. Mitzi, Byungha Shin, Teodor K. Todorov, Mark T. Winkler
  • DOUBLE LAYERED TRANSPARENT CONDUCTIVE OXIDE FOR REDUCED SCHOTTKY BARRIER IN PHOTOVOLTAIC DEVICES
    Publication number: 20180175225
    Abstract: A device and method for fabricating a photovoltaic device includes forming a double layer transparent conductive oxide on a transparent substrate. The double layer transparent conductive oxide includes forming a doped electrode layer on the substrate, and forming a buffer layer on the doped electrode layer. The buffer layer includes an undoped or p-type doped intrinsic form of a same material as the doped electrode layer. A light-absorbing semiconductor structure includes a p-type semiconductor layer on the buffer layer, an intrinsic layer and an n-type semiconductor layer.
    Type: Application
    Filed: February 12, 2018
    Publication date: June 21, 2018
    Inventors: SHUN-MING CHEN, CHIEN-CHIH HUANG, JOEL P. DESOUZA, AUGUSTIN J. HONG, JEEHWAN KIM, CHIEN-YEH KU, DEVENDRA K. SADANA, CHUAN-WEN WANG
  • Reduction of defect induced leakage in III-V semiconductor devices
    Patent number: 10002929
    Abstract: A semiconductor device includes a semiconductor substrate and a p-doped layer formed on the substrate having a dislocation density exceeding 108 cm?2. An n-type layer is formed on or in the p-doped layer. The n-type layer includes a II-VI material configured to tolerate the dislocation density to form an electronic device with reduced leakage current over a device with a III-V n-type layer.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: June 19, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joel P. de Souza, Jeehwan Kim, Devendra K. Sadana, Brent A. Wacaser
  • Resonant cavity strained III-V photodetector and LED on silicon substrate
    Patent number: 9991417
    Abstract: An optoelectronic device that includes a germanium containing buffer layer atop a silicon containing substrate, and a first distributed Bragg reflector stack of III-V semiconductor material layers on the buffer layer. The optoelectronic device further includes an active layer of III-V semiconductor material present on the first distributed Bragg reflector stack, wherein a difference in lattice dimension between the active layer and the first distributed brag reflector stack induces a strain in the active layer. A second distributed Bragg reflector stack of III-V semiconductor material layers having a may be present on the active layer.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: June 5, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jeehwan Kim, Ning Li, Devendra K. Sadana
  • Systems and methods for fabricating single-crystalline diamond membranes
    Patent number: 9991113
    Abstract: A buffer layer is employed to fabricate diamond membranes and allow reuse of diamond substrates. In this approach, diamond membranes are fabricated on the buffer layer, which in turn is disposed on a diamond substrate that is lattice-matched to the diamond membrane. The weak bonding between the buffer layer and the diamond substrate allows ready release of the fabricated diamond membrane. The released diamond membrane is transferred to another substrate to fabricate diamond devices, while the diamond substrate is reused for another fabrication.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: June 5, 2018
    Assignee: Massachusetts Institute of Technology
    Inventors: Jeehwan Kim, Dirk Robert Englund, Mark A. Hollis, Travis Wade, Michael Geis, Richard Molnar
  • POROUS SILICON RELAXATION MEDIUM FOR DISLOCATION FREE CMOS DEVICES
    Publication number: 20180138095
    Abstract: A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.
    Type: Application
    Filed: December 21, 2017
    Publication date: May 17, 2018
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Jeehwan Kim, Juntao Li, Devendra K. Sadana
  • POROUS SILICON RELAXATION MEDIUM FOR DISLOCATION FREE CMOS DEVICES
    Publication number: 20180122712
    Abstract: A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.
    Type: Application
    Filed: December 19, 2017
    Publication date: May 3, 2018
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Jeehwan Kim, Juntao Li, Devendra K. Sadana
  • TRANSPARENT CONDUCTIVE ELECTRODE FOR THREE DIMENSIONAL PHOTOVOLTAIC DEVICE
    Publication number: 20180108790
    Abstract: A photovoltaic device includes a substrate layer having a plurality of three-dimensional structures formed therein providing a textured profile. A first electrode is formed over the substrate layer and extends over the three-dimensional structures including non-planar surfaces. The first electrode has a thickness configured to maintain the textured profile, and the first electrode includes a transparent conductive material having a dopant metal activated within the transparent conductive material. A continuous photovoltaic stack is conformally formed over the first electrode, and a second electrode is formed on the photovoltaic stack.
    Type: Application
    Filed: December 19, 2017
    Publication date: April 19, 2018
    Inventors: Keith E. Fogel, Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana
  • Selective epitaxy using epitaxy-prevention layers
    Patent number: 9947533
    Abstract: A method for forming an epitaxial structure includes providing a two-dimensional material on a crystal semiconductor material and opening up portions of the two-dimensional material to expose the crystal semiconductor material. A structure is epitaxially grown in the portions opened up in the crystal semiconductor material such that the epitaxial growth is selective to the exposed crystal semiconductor material relative to the two-dimensional material.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: April 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Jeehwan Kim, John A. Ott, Devendra K. Sadana
  • Porous fin as compliant medium to form dislocation-free heteroepitaxial films
    Patent number: 9947529
    Abstract: A method for forming a heteroepitaxial layer includes forming an epitaxial grown layer on a monocrystalline substrate and patterning the epitaxial grown layer to form fins. The fins are converted to porous fins. A surface of the porous fins is treated to make the surface suitable for epitaxial growth. Lattice mismatch is compensated for between an epitaxially grown monocrystalline layer grown on the surface and the monocrystalline substrate by relaxing the epitaxially grown monocrystalline layer using the porous fins to form a relaxed heteroepitaxial interface with the monocrystalline substrate.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: April 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana
  • Transparent conductive electrode for three dimensional photovoltaic device
    Patent number: 9935215
    Abstract: A photovoltaic device includes a substrate layer having a plurality of three-dimensional structures formed therein providing a textured profile. A first electrode is formed over the substrate layer and extends over the three-dimensional structures including non-planar surfaces. The first electrode has a thickness configured to maintain the textured profile, and the first electrode includes a transparent conductive material having a dopant metal activated within the transparent conductive material. A continuous photovoltaic stack is conformally formed over the first electrode, and a second electrode is formed on the photovoltaic stack.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: April 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Keith E. Fogel, Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana
  • Porous silicon relaxation medium for dislocation free CMOS devices
    Patent number: 9929060
    Abstract: A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: March 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Jeehwan Kim, Juntao Li, Devendra K. Sadana
  • Buffer layer for high performing and low light degraded solar cells
    Patent number: 9917220
    Abstract: Methods for forming a photovoltaic device include forming a buffer layer between a transparent electrode and a p-type layer. The buffer layer includes a doped germanium-free silicon base material. The buffer layer has a work function that falls within barrier energies of the transparent electrode and the p-type layer. An intrinsic layer and an n-type layer are formed on the p-type layer. Devices are also provided.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: March 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Augustin J. Hong, Marinus J. Hopstaken, Jeehwan Kim, John A. Ott, Devendra K. Sadana