Patents by Inventor Ji Hoon Choi

Ji Hoon Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10892278
    Abstract: A three-dimensional semiconductor device includes gate electrodes sequentially stacked on a substrate, a channel structure penetrating the gate electrodes and being connected to the substrate, an insulating gap-fill pattern provided within the channel structure and surrounded by the channel structure as viewed in a plan view, and a conductive pattern on the insulating gap-fill pattern. At least a portion of the insulating gap-fill pattern is received in the conductive pattern, and at least a portion of the conductive pattern is interposed between at least that portion of the insulating gap-fill pattern and the channel structure.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: January 12, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Hoon Choi, Sunggil Kim, Seulye Kim, Hongsuk Kim, Phil Ouk Nam, Jaeyoung Ahn
  • Patent number: 10865513
    Abstract: Disclosed is a washing machine and a home appliance including a plurality of doors, a damper configured to buffer pivoting of the plurality of doors, and a structure by which each of the plurality of doors smoothly opened/shut.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: December 15, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae Sin Kim, Wan Gi Park, Kab Jin Jun, Jung Hwan Kim, Dong Ik Lee, Ji Hoon Choi
  • Patent number: 10756185
    Abstract: A semiconductor device includes a substrate, a plurality of gate electrodes extending in a first direction parallel to an upper surface of a substrate on the substrate, and alternately arranged with an interlayer insulating layer in a second direction perpendicular to the upper surface of the substrate, a vertical channel layer on a sidewall of a vertical channel hole extending in the second direction by penetrating through the plurality of gate electrodes and the interlayer insulating layer, and connected to the upper surface of the substrate, and a first gap-fill insulating layer formed in the vertical channel hole and including an outer wall contacting the vertical channel layer and an inner wall opposite the outer wall, wherein a part of the inner wall forms a striation extending in the second direction.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: August 25, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-hoon Choi, Hong-suk Kim, Sung-gil Kim, Phil-ouk Nam, Seul-ye Kim, Han-jin Lim, Jae-young Ahn
  • Publication number: 20200266213
    Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.
    Type: Application
    Filed: May 8, 2020
    Publication date: August 20, 2020
    Inventors: Ji Hoon CHOI, Sung Gil KIM, Seulye KIM, Jung Ho KIM, Hong Suk KIM, Phil Ouk NAM, Jae Young AHN, Han Jin LIM
  • Publication number: 20200243558
    Abstract: A semiconductor device may include a substrate, an electrode structure including electrodes stacked on the substrate, an upper semiconductor pattern penetrating at least a portion of the electrode structure, and a lower semiconductor pattern between the substrate and the upper semiconductor pattern. The upper semiconductor pattern includes a gap-filling portion and a sidewall portion extending from the gap-filling portion in a direction away from the substrate, the lower semiconductor pattern includes a concave top surface, the gap-filling portion fills a region enclosed by the concave top surface, a top surface of the gap-filling portion has a rounded shape that is deformed toward the substrate, and a thickness of the sidewall portion is less than a thickness of the gap-filling portion.
    Type: Application
    Filed: April 10, 2020
    Publication date: July 30, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ji-Hoon CHOI, Sunggil KIM, Seulye KIM, HongSuk KIM, Phil Ouk NAM, Jaeyoung AHN
  • Publication number: 20200176467
    Abstract: A vertical memory device may include a channel connecting pattern on a substrate, gate electrodes spaced apart from each other in a first direction on the channel connecting pattern, and a channel extending in the first direction through the gate electrodes and the channel connecting pattern. Each of the electrodes may extend in a second direction substantially parallel to an upper surface of the substrate, and the first direction may be substantially perpendicular to the upper surface of the substrate. An end portion of the channel connecting pattern in a third direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the second direction may have an upper surface higher than an upper surface of other portions of the channel connecting pattern except for a portion thereof adjacent the channel.
    Type: Application
    Filed: July 19, 2019
    Publication date: June 4, 2020
    Inventors: Ji-Hoon Choi, Sung-Gil Kim, Jung-Hwan Kim, Chan-Hyoung Kim, Woo-Sung Lee
  • Patent number: 10651194
    Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: May 12, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji Hoon Choi, Sung Gil Kim, Seulye Kim, Jung Ho Kim, Hong Suk Kim, Phil Ouk Nam, Jae Young Ahn, Han Jin Lim
  • Patent number: 10651191
    Abstract: A semiconductor device may include a substrate, an electrode structure including electrodes stacked on the substrate, an upper semiconductor pattern penetrating at least a portion of the electrode structure, and a lower semiconductor pattern between the substrate and the upper semiconductor pattern. The upper semiconductor pattern includes a gap-filling portion and a sidewall portion extending from the gap-filling portion in a direction away from the substrate, the lower semiconductor pattern includes a concave top surface, the gap-filling portion fills a region enclosed by the concave top surface, a top surface of the gap-filling portion has a rounded shape that is deformed toward the substrate, and a thickness of the sidewall portion is less than a thickness of the gap-filling portion.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: May 12, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Hoon Choi, Sunggil Kim, Seulye Kim, HongSuk Kim, Phil Ouk Nam, Jaeyoung Ahn
  • Patent number: 10651500
    Abstract: The present invention relates to a positive electrode active material for a secondary battery, a method for preparing the same, and a secondary battery including the same, and more particularly to a positive electrode active material for a secondary battery, which includes lithium transition metal oxide particles represented by Formula 1; and lithium metal phosphate nanoparticles disposed on the surface of the lithium transition metal oxide particles and represented by Formula 2, a method for preparing the same, and a lithium secondary battery including the same Li(1+a)(Ni1?b?cMbCoc)O2??[Formula 1] In which, M is at least one metal selected from the group consisting of Mn, Al, Cu, Fe, Mg, Cr, Sr, V, Sc and Y, 0?a?0.2, 0?b?1, and 0?c?1 Li1+xM?xM?2?x(PO4)3??[Formula 2] In which, M? is Al, Y, Cr, or Ca, M? is Ge, Ti, Sn, Hf, Zn, or Zr, and 0?x?0.5.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: May 12, 2020
    Assignee: LG Chem, Ltd.
    Inventors: Ji Hoon Choi, In Kook Jun, Seung Beom Cho
  • Patent number: 10600806
    Abstract: A stack structure includes conductive layer patterns and interlayer insulating layer patterns alternately stacked on one another. A channel hole penetrates the stack structure. A dielectric layer is disposed on a sidewall of the channel hole. A channel layer is disposed on the dielectric layer and in the channel hole. A passivation layer is disposed on the channel layer and in the channel hole. The channel layer is interposed between the passivation layer and the dielectric layer. An air gap is surrounded by the passivation layer. A width of the air gap is larger than a width of the passivation layer.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: March 24, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Gil Kim, Seul Ye Kim, Hong Suk Kim, Jin Tae Noh, Ji Hoon Choi, Jae Young Ahn
  • Patent number: 10526742
    Abstract: A washing machine includes a plurality of suspension units through which a tub is supported by a cabinet, and a stabilizer unit mounted to the tub. When horizontal vibration displacement of the tub occurs by unbalance mass during washing/dehydration processes, the washing machine limits tub displacement according to the attenuation effect caused by torsional force and bending force of the stabilizer unit, resulting in reduction of excessive vibration.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: January 7, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung Oh Kim, Young Myung Son, Marenne Pierre, Ji Hoon Choi
  • Publication number: 20190393489
    Abstract: A cathode active material for a lithium secondary battery includes a lithium-aluminum-titanium oxide formed on a surface of a lithium metal oxide particle having a specific formula. The cathode active material may have an improved structural stability even in a high temperature condition.
    Type: Application
    Filed: April 30, 2019
    Publication date: December 26, 2019
    Inventors: Mi Jung NOH, Jik Soo KIM, Sang Bok KIM, Ji Hoon CHOI, Kook Hyun HAN
  • Patent number: 10501881
    Abstract: Disclosed herein is a washing machine including a damping device to be operable according to vibration displacement. In a washing machine including a damping device provided to damp a vibration transferred from a washing tub, the damping device includes a suspension member, a damping unit provided to move along the suspension member, and a friction unit provided in the damping unit to form a frictional force with the suspension member, and the friction unit is disposed while being spaced apart from an inner surface of the damping unit to be selectively movable depending on a level of the vibration of the washing tub.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: December 10, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Ha Jung, Kab Jin Jun, Jeong Hoon Kang, Ji Hoon Choi, Sang Young Kweon
  • Publication number: 20190333937
    Abstract: A three-dimensional semiconductor device includes gate electrodes sequentially stacked on a substrate, a channel structure penetrating the gate electrodes and being connected to the substrate, an insulating gap-fill pattern provided within the channel structure and surrounded by the channel structure as viewed in a plan view, and a conductive pattern on the insulating gap-fill pattern. At least a portion of the insulating gap-fill pattern is received in the conductive pattern, and at least a portion of the conductive pattern is interposed between at least that portion of the insulating gap-fill pattern and the channel structure.
    Type: Application
    Filed: July 11, 2019
    Publication date: October 31, 2019
    Inventors: JI-HOON CHOI, SUNGGIL KIM, SEULYE KIM, HONGSUK KIM, PHIL OUK NAM, JAEYOUNG AHN
  • Publication number: 20190326321
    Abstract: A stack structure includes conductive layer patterns and interlayer insulating layer patterns alternately stacked on one another. A channel hole penetrates the stack structure. A dielectric layer is disposed on a sidewall of the channel hole. A channel layer is disposed on the dielectric layer and in the channel hole. A passivation layer is disposed on the channel layer and in the channel hole. The channel layer is interposed between the passivation layer and the dielectric layer. An air gap is surrounded by the passivation layer. A width of the air gap is larger than a width of the passivation layer.
    Type: Application
    Filed: July 1, 2019
    Publication date: October 24, 2019
    Inventors: Sung Gil KIM, Seul Ye KIM, Hong Suk KIM, Jin Tae NOH, Ji Hoon CHOI, Jae Young AHN
  • Patent number: 10453745
    Abstract: A semiconductor device is provided. The semiconductor device includes a stack structure comprising insulating patterns and electrode structures alternately stacked on a substrate, and a vertical channel structure vertically penetrating the stack structure. Each of the electrode structures includes a conductive pattern having a first sidewall and a second sidewall opposite to the first sidewall, a first etching prevention pattern on the first sidewall, and a second etching prevention pattern on the second sidewall.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: October 22, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-Hoon Choi, Jung Ho Kim, Dongkyum Kim, Seulye Kim, Jintae Noh, Hyun-Jin Shin, SeungHyun Lim
  • Publication number: 20190275907
    Abstract: Disclosed are a charger and a method of charging an electric vehicle. A main body of the charger includes a plurality of sub main bodies coupled to each other to transform its shape. The charger with the main body having a first shape moves toward the electric vehicle, and is then transformed to have a second shape. The first shape refers to a shape allowing the main body to be movable on a ground, and the second shape refers to a shape making the main body occupy a smaller surrounding area of the electric vehicle than the first shape. The electric vehicle is charged as connected to the charger having the second shape. The charger does not obstruct traffic of other vehicles because its size is reduced during charging.
    Type: Application
    Filed: June 9, 2017
    Publication date: September 12, 2019
    Inventors: Hun LEE, Cheol-hoi KIM, Ji-hoon CHOI
  • Patent number: 10403641
    Abstract: A semiconductor device may include a plurality of conductive patterns and an insulation pattern. The plurality of conductive patterns may be formed on a substrate. The plurality of conductive patterns may be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate. Each of the plurality of conductive patterns may have an extension portion and a step portion. The step portion may be disposed at an edge of the corresponding conductive pattern. The insulation pattern may be formed between the plurality of conductive patterns in the vertical direction. A lower surface and an upper surface of the step portion of each of the plurality of conductive patterns may be bent upwardly.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: September 3, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Gil Kim, Seul-Ye Kim, Hong-suk Kim, Phil-Ouk Nam, Jae-Young Ahn, Ji-Hoon Choi
  • Patent number: 10396094
    Abstract: A three-dimensional semiconductor device includes gate electrodes sequentially stacked on a substrate, a channel structure penetrating the gate electrodes and being connected to the substrate, an insulating gap-fill pattern provided within the channel structure and surrounded by the channel structure as viewed in a plan view, and a conductive pattern on the insulating gap-fill pattern. At least a portion of the insulating gap-fill pattern is received in the conductive pattern, and at least a portion of the conductive pattern is interposed between at least that portion of the insulating gap-fill pattern and the channel structure.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: August 27, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Hoon Choi, Sunggil Kim, Seulye Kim, Hongsuk Kim, Phil Ouk Nam, Jaeyoung Ahn
  • Publication number: 20190206886
    Abstract: A semiconductor memory device may include: a stacking structure including a plurality of insulating layers and a plurality of gate electrodes alternately stacked on a substrate; a lower semiconductor pattern that protrudes from the top of the substrate; a vertical insulating pattern that extends in a vertical direction from the substrate and penetrates the stacking structure; and a vertical channel pattern on the inner surface of the vertical insulating pattern and contacting the lower semiconductor pattern, wherein an upper part of the lower semiconductor pattern includes a recess region including a curve-shaped profile, and in the recess region, the outer surface of a lower part of the vertical channel pattern contacts the lower semiconductor pattern along a curve of the recess region.
    Type: Application
    Filed: March 11, 2019
    Publication date: July 4, 2019
    Inventors: Sung Gil Kim, Ji-Hoon Choi, Dongkyum Kim, Jintae Noh, Seulye Kim, Hong Suk Kim, Phil Ouk Nam, Jaeyoung Ahn