Abstract: A semiconductor device is provided. The semiconductor device includes a stack structure comprising insulating patterns and electrode structures alternately stacked on a substrate, and a vertical channel structure vertically penetrating the stack structure. Each of the electrode structures includes a conductive pattern having a first sidewall and a second sidewall opposite to the first sidewall, a first etching prevention pattern on the first sidewall, and a second etching prevention pattern on the second sidewall.

Abstract: Disclosed are a charger and a method of charging an electric vehicle. A main body of the charger includes a plurality of sub main bodies coupled to each other to transform its shape. The charger with the main body having a first shape moves toward the electric vehicle, and is then transformed to have a second shape. The first shape refers to a shape allowing the main body to be movable on a ground, and the second shape refers to a shape making the main body occupy a smaller surrounding area of the electric vehicle than the first shape. The electric vehicle is charged as connected to the charger having the second shape. The charger does not obstruct traffic of other vehicles because its size is reduced during charging.

Abstract: A semiconductor device may include a plurality of conductive patterns and an insulation pattern. The plurality of conductive patterns may be formed on a substrate. The plurality of conductive patterns may be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate. Each of the plurality of conductive patterns may have an extension portion and a step portion. The step portion may be disposed at an edge of the corresponding conductive pattern. The insulation pattern may be formed between the plurality of conductive patterns in the vertical direction. A lower surface and an upper surface of the step portion of each of the plurality of conductive patterns may be bent upwardly.

Abstract: A three-dimensional semiconductor device includes gate electrodes sequentially stacked on a substrate, a channel structure penetrating the gate electrodes and being connected to the substrate, an insulating gap-fill pattern provided within the channel structure and surrounded by the channel structure as viewed in a plan view, and a conductive pattern on the insulating gap-fill pattern. At least a portion of the insulating gap-fill pattern is received in the conductive pattern, and at least a portion of the conductive pattern is interposed between at least that portion of the insulating gap-fill pattern and the channel structure.

Abstract: A semiconductor memory device may include: a stacking structure including a plurality of insulating layers and a plurality of gate electrodes alternately stacked on a substrate; a lower semiconductor pattern that protrudes from the top of the substrate; a vertical insulating pattern that extends in a vertical direction from the substrate and penetrates the stacking structure; and a vertical channel pattern on the inner surface of the vertical insulating pattern and contacting the lower semiconductor pattern, wherein an upper part of the lower semiconductor pattern includes a recess region including a curve-shaped profile, and in the recess region, the outer surface of a lower part of the vertical channel pattern contacts the lower semiconductor pattern along a curve of the recess region.

Abstract: A stack structure includes conductive layer patterns and interlayer insulating layer patterns alternately stacked on one another. A channel hole penetrates the stack structure. A dielectric layer is disposed on a sidewall of the channel hole. A channel layer is disposed on the dielectric layer and in the channel hole. A passivation layer is disposed on the channel layer and in the channel hole. The channel layer is interposed between the passivation layer and the dielectric layer. An air gap is surrounded by the passivation layer. A width of the air gap is larger than a width of the passivation layer.

Abstract: A three-dimensional semiconductor memory device includes an electrode structure including electrodes vertically stacked on a semiconductor layer, a vertical semiconductor pattern penetrating the electrode structure and connected to the semiconductor layer, and a vertical insulating pattern between the electrode structure and the vertical semiconductor pattern. The vertical insulating pattern includes a sidewall portion on a sidewall of the electrode structure, and a protrusion extending from the sidewall portion along a portion of a top surface of the semiconductor layer. The vertical semiconductor pattern includes a vertical channel portion having a first thickness and extending along the sidewall portion of the vertical insulating pattern, and a contact portion extending from the vertical channel portion and conformally along the protrusion of the vertical insulating pattern and the top surface of the semiconductor layer. The contact portion has a second thickness greater than the first thickness.

Abstract: A semiconductor memory device may include: a stacking structure including a plurality of insulating layers and a plurality of gate electrodes alternately stacked on a substrate; a lower semiconductor pattern that protrudes from the top of the substrate; a vertical insulating pattern that extends in a vertical direction from the substrate and penetrates the stacking structure; and a vertical channel pattern on the inner surface of the vertical insulating pattern and contacting the lower semiconductor pattern, wherein an upper part of the lower semiconductor pattern includes a recess region including a curve-shaped profile, and in the recess region, the outer surface of a lower part of the vertical channel pattern contacts the lower semiconductor pattern along a curve of the recess region.

Abstract: A semiconductor memory device has a plurality of gates vertically stacked on a top surface of a substrate, a vertical channel filling a vertical hole that extends vertically through the plurality of gates, and a memory layer in the vertical hole and surrounding the vertical channel. The vertical channel includes a bracket-shaped lower portion filling part of a recess in the top of the substrate and an upper portion extending vertically along the vertical hole and connected to the lower channel. At least one end of an interface between the lower and upper portions of the vertical channel is disposed at a level not than that of the top surface of the substrate.

Abstract: A substrate processing apparatus including a process chamber configured to receive a plurality of substrates oriented in a horizontal manner and vertically arranged with respect to the process chamber, a process gas supply unit configured to supply at least one process gas to the process chamber through a process gas supply nozzle, the process gas supply nozzle along an inner wall of the process chamber in a direction in which the substrates are sacked, an exhaust unit configured to exhaust the process gas from the process chamber, and a blocking gas supply unit configured to supply a blocking gas through a blocking gas injector provided in a circumferential direction of the process chamber such that a flow of the process gas in the process chamber is controlled may be provided.

Abstract: Disclosed is a washing machine and a home appliance including a plurality of doors, a damper configured to buffer pivoting of the plurality of doors, and a structure by which each of the plurality of doors smoothly opened/shut.

Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.

Abstract: Disclosed is a method and apparatus for training a speech signal. A speech signal training apparatus of the present disclosure may include a target speaker speech database storing a target speaker speech signal; a multi-speaker speech database storing a multi-speaker speech signal; a target speaker acoustic parameter extracting unit extracting an acoustic parameter of a training subject speech signal from the target speaker speech signal; a similar speaker acoustic parameter determining unit extracting at least one similar speaker speech signal from the multi-speaker speech signals, and determining an auxiliary speech feature of the similar speaker speech signal; and an acoustic parameter model training unit determining an acoustic parameter model by performing model training for a relation between the acoustic parameter and text by using the acoustic parameter and the auxiliary speech feature, and setting mapping information of the relation between the acoustic parameter model and the text.

Abstract: A stack structure includes conductive layer patterns and interlayer insulating layer patterns alternately stacked on one another. A channel hole penetrates the stack structure. A dielectric layer is disposed on a sidewall of the channel hole. A channel layer is disposed on the dielectric layer and in the channel hole. A passivation layer is disposed on the channel layer and in the channel hole. The channel layer is interposed between the passivation layer and the dielectric layer. An air gap is surrounded by the passivation layer. A width of the air gap is larger than a width of the passivation layer.

Abstract: A semiconductor device may include a plurality of conductive patterns and an insulation pattern. The plurality of conductive patterns may be formed on a substrate. The plurality of conductive patterns may be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate. Each of the plurality of conductive patterns may have an extension portion and a step portion. The step portion may be disposed at an edge of the corresponding conductive pattern. The insulation pattern may be formed between the plurality of conductive patterns in the vertical direction. A lower surface and an upper surface of the step portion of each of the plurality of conductive patterns may be bent upwardly.

Abstract: The present disclosure relates to a novel tetrahydropyridine derivative compound, a stereoisomer thereof, or a pharmaceutically acceptable salt thereof, methods for preparing the compounds, methods for inhibiting UDP-3-O—(R-3-hydroxymyristoyl)-N-acetylglucosamine deacetylase (LpxC), methods for treating Gram-negative bacterial infections, the use of the compounds for the preparation of therapeutic medicaments for treating Gram-negative bacterial infections, and pharmaceutical compositions for prevention or treatment of Gram-negative bacterial infections, which contain the compounds. The compounds represented by formula I, stereoisomers thereof or pharmaceutically acceptable salts thereof according to the present disclosure can exhibit excellent effects on the treatment bacterial infections.

Abstract: A semiconductor device may include a substrate, an electrode structure including electrodes stacked on the substrate, an upper semiconductor pattern penetrating at least a portion of the electrode structure, and a lower semiconductor pattern between the substrate and the upper semiconductor pattern. The upper semiconductor pattern includes a gap-filling portion and a sidewall portion extending from the gap-filling portion in a direction away from the substrate, the lower semiconductor pattern includes a concave top surface, the gap-filling portion fills a region enclosed by the concave top surface, a top surface of the gap-filling portion has a rounded shape that is deformed toward the substrate, and a thickness of the sidewall portion is less than a thickness of the gap-filling portion.

Abstract: A three-dimensional semiconductor device includes gate electrodes sequentially stacked on a substrate, a channel structure penetrating the gate electrodes and being connected to the substrate, an insulating gap-fill pattern provided within the channel structure and surrounded by the channel structure as viewed in a plan view, and a conductive pattern on the insulating gap-fill pattern. At least a portion of the insulating gap-fill pattern is received in the conductive pattern, and at least a portion of the conductive pattern is interposed between at least that portion of the insulating gap-fill pattern and the channel structure.

Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.

Abstract: Provided is a washing machine including a rib extending outward from a central portion of a rear portion of a tub. One end of the rib is provided adjacent to the central portion of the tub, the other end of the rib is provided adjacent to an outer side of the tub, and since a width of the one end of the rib is greater than a width of the other end of the rib, thereby maintaining efficient rigidity against stress generated in the rear portion of the tub. Further, in order to secure rigidity against stress due to vibrations generated by a driving motor, an additional rib is included between a side to which the driving motor is coupled and the outer side of the tub, thereby efficiently maintaining rigidity against additional stress.