Abstract: Electronic devices and methods for their formation are described. One device relates to an electronic assembly including a substrate having a first surface and a second surface opposite the first surface. The electronic assembly also includes at least one RF front-end module coupled to the first surface of the substrate, and a ground plane layer positioned on the second surface of the substrate. The electronic assembly also includes an insulating layer on the ground plane layer, with the ground plane layer positioned between the second surface and the insulating layer. In addition, the electronic assembly also includes an antenna layer on the insulating layer, with the insulating layer positioned between the antenna layer and the ground plane layer.

Abstract: An integrated circuit with reduced pad capacitance, having a trench formed in the silicon substrate below the pad to reduce the pad capacitance. In another embodiment, an encapsulated air cavity if formed underneath the pad. Other embodiments are described and claimed.

Abstract: Some embodiments of the present invention include apparatuses and methods relating to integrated micro-channels for removing heat from 3D through silicon architectures.

Abstract: Transmission line impedance matching for matching an impedance discontinuity on a transmission signal trace with one or more non-transmission traces disposed near the transmission signal trace at a region corresponding to the impedance discontinuity.

Abstract: Trace configurations for carrying high-speed digital differential signals provide for reduced conduction loss and improved signal integrity. In one embodiment, a circuit board has a first set of conductive traces disposed on non-conductive material, and a second set of conductive traces parallel to the first set and disposed within the conductive material. The second set is separated from the first set by non-conductive material. Corresponding traces of the first and second sets may be in a stacked configuration. In other embodiments, conductive material may be provided between corresponding traces of the first and second sets resulting in an “I-shaped” or “U-shaped” cross-section. In yet other embodiments, the trace configurations have “T-shaped” and “L-shaped” cross-sections.

Abstract: A method of forming a package, comprising providing a set of dies on a substrate. The substrate may have a first die on its upper side and a second die on its lower side. A first interconnect may be provided in the substrate, wherein the first interconnect penetrates through the substrate to couple the dies to the substrate.

Abstract: Electronic devices and methods for their formation are described. One device relates to an electronic assembly including a substrate having a first surface and a second surface opposite the first surface. The electronic assembly also includes at least one RF front-end module coupled to the first surface of the substrate, and a ground plane layer positioned on the second surface of the substrate. The electronic assembly also includes an insulating layer on the ground plane layer, with the ground plane layer positioned between the second surface and the insulating layer. In addition, the electronic assembly also includes an antenna layer on the insulating layer, with the insulating layer positioned between the antenna layer and the ground plane layer.

Abstract: A package may comprise a substrate provided with noise absorbing material. The noise absorbing material may absorb noise from a signal path in the substrate to prevent the noise from reaching other signals or signal paths.

Abstract: A conductive path, such as a copper patch, between decoupling capacitors and a high frequency integrated circuit, may be oxidized to improve the power delivery performance. Specifically, adding the resistance in the conductive path by oxidizing the conductive path increases the dampening of the peak impedance at a given peak frequency. In some embodiments, a mask may be used to control the amount of the conductive path that is oxidized.

Abstract: Embodiments of the present invention include an apparatus, method, and/or system for an integrated circuit package with signal connections on the chip-side of the package structure.

Abstract: A chip-to-chip optical interconnect includes a substrate, an optoelectronic die, and a waveguide structure. The substrate includes an optical via passing through the substrate. The optoelectronic die is disposed on the substrate and aligned to optically communicate through the optical via. A waveguide structure is positioned proximate to the substrate and aligned with the optical via to communicate optical signals with the optoelectronic die through the optical via.

Abstract: In one embodiment, the present invention includes a semiconductor package with lossy material inserts. The lossy material inserts may reduce electronic noise such as package resonance. Other embodiments are described and claimed.

Abstract: A circuit package may include an upper surface of first conductive elements and second conductive elements. The first conductive elements may receive input/output signals from respective conductive elements of an integrated circuit die, and the second conductive elements may receive a first plurality of the input/output signals from respective ones of the first conductive elements. A lower surface of the package may include third conductive elements, the third conductive elements to receive a second plurality of the input/output signals from respective other ones of the first conductive elements.

Abstract: A method includes mating a first heat spreader and a second heat spreader, such that the first heat spreader at a mating surface and second heat spreader at a mating surface become parallel and adjacent. The mated first heat spreader and second heat spreader have at least one convection channel disposed therebetween. A process includes placing a first die in a first die recess of the first heat spreader, and placing a second die on a second die site on the second heat spreader. The process includes reflowing thermal interface material between each die and respective heat spreader. A package is achieved by the method, with reduced thicknesses. The package can be coupled through a bumpless build-up layer. The package can be assembled into a computing system.

Abstract: An apparatus and system, as well as fabrication methods therefor, may include a plurality of vertically-oriented plates separated by dielectric layers, wherein the vertically-oriented plates include a plurality of terminals coupled to a bottom side of the plates.

Abstract: An apparatus for filtering noise from an input/output (I/O) signal is disclosed. In various embodiments, the apparatus may be an array capacitor, and may be disposed between an electronic package and an underlying substrate such as a printed circuit board.

Abstract: A system may include a microprocessor die, an integrated circuit package substrate, and a die disposed between the microprocessor die and the integrated circuit package substrate. In some embodiments, the integrated circuit package substrate defines a first cavity, and the die is disposed at least partially within the first cavity.

Abstract: Embodiments of the present invention include an apparatus, method, and/or system for an integrated circuit package with signal connections on the chip-side of the package structure.

Abstract: A process includes mating a first heat spreader and a second heat spreader, such that the first heat spreader at a mating surface and second heat spreader at a mating surface become parallel and adjacent. The process includes placing a first die in a first die recess of the first heat spreader, and placing a second die in a second die recess in the second heat spreader. The process includes reflowing thermal interface material between each die and respective heat spreader. Thereafter, the process includes separating the first heat spreader and the second heat spreader. A package is achieved by the process, with reduced thicknesses. The package can be disposed onto a mounting substrate. The package can be assembled into a computing system.

Abstract: An integrated circuit (“IC”) package having two or more dice stacked on a substrate and electrically coupled using two or more different connection technologies may improve high-speed input/output (“I/O”) bandwidth. In an embodiment, one die is a processor and at least one other die is a dynamic random access memory (“DRAM”). One or more of the dice may be thinned and placed between the substrate and a portion of one or more of the other dice, which may be horizontally offset. One or more of the dice may be embedded in the substrate. The dice may be coupled to each other and to the substrate using a combination of controlled-collapse chip connection (“C4”) and wirebonding connection technologies. Methods of fabrication, and application of the package to an electronic assembly and to an electronic system, are also described.