Abstract: Some embodiments of the present invention include apparatuses and methods relating to integrated micro-channels for removing heat from 3D through silicon architectures.

Abstract: An improved silicon building block is disclosed. In an embodiment, the silicon building block has at least two vias through it. The silicon building block is doped and the vias filled with a first material, and, optionally, selected ones of the vias filled instead with a second material. In an alternative embodiment, regions of the silicon building block have metal deposited on them.

Abstract: An inter-digital capacitor may be used in a power socket for a microelectronic device. In one embodiment an integrated, low-resistance power and ground terminal configuration is disclosed. The capacitor plates are alternatively coupled to the power and ground terminals. Two polarity types are disclosed. A method of operation is also described.

Abstract: A method to reduce parasitic mutual capacitances in embedded passives. A first capacitor is formed by first and second electrodes embedding a dielectric layer. A second capacitor is formed by third and fourth electrodes embedding the dielectric layer. The third and first electrodes are etched from a first metal layer. The fourth and second electrodes are etched from a second metal layer. The first and the fourth electrodes are connected by a connection through the dielectric layer to shield a mutual capacitance between the first and second capacitors.

Abstract: Trace configurations for carrying high-speed digital differential signals provide for reduced conduction loss and improved signal integrity. In one embodiment, a circuit board has a first set of conductive traces disposed on non-conductive material, and a second set of conductive traces parallel to the first set and disposed within the conductive material. The second set is separated from the first set by non-conductive material. Corresponding traces of the first and second sets may be in a stacked configuration. In other embodiments, conductive material may be provided between corresponding traces of the first and second sets resulting in an “I-shaped” or “U-shaped” cross-section. In yet other embodiments, the trace configurations have “T-shaped” and “L-shaped” cross-sections.

Abstract: Transmission line impedance matching is described for matching an impedance discontinuity on a transmission signal trace. The apparatus includes a transmission signal trace and a non-transmission trace. The transmission signal trace has an impedance discontinuity, a first length, and a predetermined first width. The non-transmission trace is disposed near the transmission signal trace at a region corresponding to the impedance discontinuity. The non-transmission trace has a second length that is substantially less than the first length of the transmission signal trace. Additionally, the non-transmission trace is configured to be electromagnetically coupled to the transmission signal trace in the presence of a current on the transmission signal trace to provide a matched impedance on the transmission signal trace.

Abstract: Trace configurations for carrying high-speed digital differential signals provide for reduced conduction loss and improved signal integrity. In one embodiment, a circuit board has a first set of conductive traces disposed on non-conductive material, and a second set of conductive traces parallel to the first set and disposed within the conductive material. The second set is separated from the first set by non-conductive material. Corresponding traces of the first and second sets may be in a stacked configuration. In other embodiments, conductive material may be provided between corresponding traces of the first and second sets resulting in an “I-shaped” or “U-shaped” cross-section. In yet other embodiments, the trace configurations have “T-shaped” and “L-shaped” cross-sections.

Abstract: A capacitor has at least one plate of a first polarity and at least two plates of a second polarity, with a terminal electrically connected to the at least two plates of the second polarity such that the electrical plate connections are remote from an edge of the connected plates.

Abstract: Extending high k material of a second dielectric layer to surround at least one thru-via designed to provide a signal other than a power signal to a die may eliminate discrete AC coupling capacitors to reduce cost and improve performance of the package.

Abstract: An apparatus comprises a signal layer including a first and second signal trace. The apparatus also comprises a first reference plane including a first slot substantially parallel to the first and second signal traces. Further, the apparatus includes a dielectric layer having at least a portion disposed between the signal layer and the first reference plane.

Abstract: In one embodiment, an integrated circuit package comprises a substrate including a first surface having a plurality of signal land pads and a second surface having a plurality of signal die pads; a plurality of signal connectors arranged to electrically couple the plurality of the signal land pads to the plurality of the signal die pads; and a ground plane, disposed in an adjacent, spaced-apart relationship to the plurality of signal land pads. The ground plane includes a plurality of holes with at least one of the holes having at least one of the signal connectors extending therethrough and being dimensioned and configured approximately to be as large or larger than at least one of the signal land pads disposed adjacent to the at least one hole.

Abstract: Methods of forming a microelectronic structure are described. Those methods comprise depositing a bottom electrode, depositing a dielectric layer on the bottom electrode, forming at least one via in the dielectric layer, wherein a bottom surface of the via does not contact a top surface of the bottom electrode, and depositing a top electrode on the dielectric layer.

Abstract: Methods of forming a microelectronic structure are described. Those methods comprise depositing a bottom electrode, depositing a dielectric layer on the bottom electrode, forming at least one via in the dielectric layer, wherein a bottom surface of the via does not contact a top surface of the bottom electrode, and depositing a top electrode on the dielectric layer.

Abstract: Extending high k material of a second dielectric layer to surround at least one thru-via designed to provide a signal other than a power signal to a die may eliminate discrete AC coupling capacitors to reduce cost and improve performance of the package.

Abstract: An apparatus for filtering noise from an input/output (I/O) signal is disclosed. In various embodiments, the apparatus may be an array capacitor, and may be disposed between an electronic package and an underlying substrate such as a printed circuit board.

Abstract: Some embodiments of the present invention include integrated inductors and compliant interconnects for semiconductor packaging.

Abstract: An apparatus is constituted with an integrated circuit and a flex tape coupled to the integrated circuit. The flex tape is employed to facilitate ingress/egress of signals to/from the integrated circuit. In one embodiment, the flex tape includes a plurality of signal traces. In another embodiment, the apparatus also includes a silicon interposer coupled to the flex tape and a substrate coupled to the silicon interposer.

Abstract: An apparatus is constituted with an integrated circuit and a flex tape coupled to the integrated circuit. The flex tape is employed to facilitate ingress/egress of signals to/from the integrated circuit. In one embodiment, the flex tape includes a plurality of signal-traces. In another embodiment, the apparatus also includes a silicon interposer coupled to the flex tape and a substrate coupled to the silicon interposer.

Abstract: According to embodiments of the present invention, a balun is disposed on a package that is to receive a die. In embodiments, the balun includes a first metal trace disposed on a first base and a second metal trace disposed on a second base. In embodiments, the first metal trace is one-quarter wavelength of an operating wavelength for a radio frequency (RF) signal and the second metal trace is three-quarters wavelength of the wavelength.

Abstract: Transmission line impedance matching is described for matching an impedance discontinuity on a transmission signal trace. The apparatus includes a transmission signal trace and a non-transmission trace. The transmission signal trace has an impedance discontinuity, a first length, and a predetermined first width. The non-transmission trace is disposed near the transmission signal trace at a region corresponding to the impedance discontinuity. The non-transmission trace has a second length that is substantially less than the first length of the transmission signal trace. Additionally, the non-transmission trace is configured to be electromagnetically coupled to the transmission signal trace in the presence of a current on the transmission signal trace to provide a matched impedance on the transmission signal trace.