Abstract: A chip-to-chip optical interconnect includes a substrate, an optoelectronic die, and a waveguide structure. The substrate includes an optical via passing through the substrate. The optoelectronic die is disposed on the substrate and aligned to optically communicate through the optical via. A waveguide structure is positioned proximate to the substrate and aligned with the optical via to communicate optical signals with the optoelectronic die through the optical via.

Abstract: Some embodiments of the present invention include integrated inductors and compliant interconnects for semiconductor packaging.

Abstract: Some embodiments of the present invention include integrated inductors and compliant interconnects for semiconductor packaging.

Abstract: Transmission line impedance matching for matching an impedance discontinuity on a transmission signal trace with one or more non-transmission traces disposed near the transmission signal trace at a region corresponding to the impedance discontinuity.

Abstract: Data signal interconnections are described that offer reduced cross talk particularly with high speed differential signaling. In one example, the invention includes a plurality of interconnects to carry data signals between a first component and a second component, the plurality of interconnects including a first set of interconnects oriented in a first direction and a second set of interconnects oriented in a second direction, different from the first direction.

Abstract: Electronic devices and methods for fabricating electronic devices are described. One embodiment includes an electronic device having a first die, the first die having a top surface, a bottom surface, and a plurality of side surfaces. The first die also includes a plurality of metal pads on the top surface extending to an outer edge of the top surface, and a plurality of metal pads on the bottom surface extending to an outer edge of the bottom surface. The first die also includes a plurality of metal regions along the side surfaces, wherein each of the metal regions extends between one of the metal pads on the top surface and one of the metal pads on the bottom surface. Other embodiments are described and claimed.

Abstract: An article includes a top electrode that is embedded in a solder mask. An article includes a top electrode that is on a core structure. A process of forming the top electrode includes reducing the solder mask thickness and forming the top electrode on the reduced-thickness solder mask. A process of forming the top electrode includes forming the top electrode over a high-K dielectric that is in a patterned portion of the core structure.

Abstract: A separable electrical connection may be provided with a landside pad on one of two electrical components to be joined. The landside pad may be made up of two parts, including a flat portion and a raised edge formed on the flat portion. In some embodiments, the raised edge may have a closed geometric shape. Then, a socket contact engaging the junction between the flat portion and the raised edge is prevented from sliding off of the landside pad by the raised edge. In addition, dual areas of electrical connection can be established between both the flat portion and raised edge of the landside pad and the correspondingly shaped pair of portions on the socket. This increases the electrical efficiency of the connection and its security.

Abstract: Data signal interconnections are described that offer reduced cross talk particularly with high speed differential signaling.

Abstract: The formation of electronic assemblies including a heat spreader coupled to at least one die is described. One embodiment relates to a method including positioning a solder on a heat spreader. The method also includes forming a solid state diffusion bond between the solder and the heat spreader. The solid state diffusion bonded solder and heat spreader are positioned on a die and heated to a temperature sufficient to melt the solder and form a bond between the solder and the die, in the absence of a flux. Other embodiments are described and claimed.

Abstract: A spiral inductor is disposed above a substrate that includes two different materials. A dielectric film is the first material that provides structural integrity for the substrate. A second dielectric is the second material that provides a low dielectric-constant (low-K) material closest to the spiral inductor coil. A process of forming the spiral inductor includes patterning the substrate to allow a recess as a receptacle for the second dielectric, followed by forming the spiral inductor mostly above the second dielectric.

Abstract: Embodiments of the invention relate to the construction of a dual die package with a high-speed interconnect. A package is created having a first die on a first side of a base substrate and a second die on a second side of the base substrate in opposed relation to the first die. A first copper plated interconnect is plated to the base substrate. Second copper interconnects are formed to connect the first copper plated interconnect to the first and second dice, respectively, such that the first and second dice are interconnected.

Abstract: Complementary inductor structures. The inductor structure may include two or more sub-inductors that have positive coupling to provide a total inductance approximately equal to the sum of the inductance provided by the two or more sub-inductors. Radiation from the two or more sub-inductors may be in different phases to partially, or even totally, cancel and result in a reduced overall radiation, which may reduce electromagnetic interference and/or electromagnetic coupling.

Abstract: A method including modifying a characteristic impedance along a length of a plating bar of a substrate package. An apparatus including a package substrate including a plurality of transmission lines therethrough, a portion of the plurality of transmission lines each including a plating bar coupled thereto, wherein the plating bar comprises portions having different characteristic impedance along its length. A system including a computing device including a microprocessor, the microprocessor coupled to a printed circuit board through a substrate, the substrate including a plurality of transmission lines therethrough, a portion of the plurality of transmission lines each including a plating bar coupled thereto, wherein the plating bar comprises portions having different characteristic impedance along its length.

Abstract: A system may include a microprocessor die, an integrated circuit package substrate, and a die disposed between the microprocessor die and the integrated circuit package substrate. In some embodiments, the integrated circuit package substrate defines a first cavity, and the die is disposed at least partially within the first cavity.

Abstract: In one embodiment, the present invention includes a semiconductor package having a substrate with a first surface to support a semiconductor die. A second surface of the substrate includes compliant conductive pads to provide electrical connections to the semiconductor die. In this way, improved connection between the semiconductor package and a socket is provided. Other embodiments are described and claimed.

Abstract: In one embodiment, an integrated circuit package comprises a substrate including a first surface having a plurality of signal land pads and a second surface having a plurality of signal die pads; a plurality of signal connectors arranged to electrically couple the plurality of the signal land pads to the plurality of the signal die pads; and a ground plane, disposed in an adjacent, spaced-apart relationship to the plurality of signal land pads. The ground plane includes a plurality of holes with at least one of the holes having at least one of the signal connectors extending therethrough and being dimensioned and configured approximately to be as large or larger than at least one of the signal land pads disposed adjacent to the at least one hole.

Abstract: Transmission line impedance matching for matching an impedance discontinuity on a transmission signal trace with one or more non-transmission traces disposed near the transmission signal trace at a region corresponding to the impedance discontinuity.

Abstract: Disclosed are embodiments of a multi-chip assembly including optically coupled die. The multi-chip assembly may include two opposing substrates, and a number of die are mounted on each of the substrates. At least one die on one of the substrates is in optical communication with at least one opposing die on the other substrate. Other embodiments are described and claimed.

Abstract: Some embodiments provide a first portion of an inductor disposed in a first layer of a multilayer substrate, a second portion of the inductor disposed in a second layer of the multilayer substrate, the second portion coupled to the first portion, and a shielding plane disposed between the first portion and the second portion.