Abstract: A reference potential adjusting apparatus is provided. The reference potential adjusting apparatus includes a reference potential measuring unit configured to measure a potential of a solution, a counter electrode disposed in the solution, and configured to change the potential of the solution through oxidation-reduction reactions with the solution, and a comparator configured to compare a measurement voltage provided by the reference voltage measuring unit to a reference voltage provided by a reference voltage supply unit, and to adjust reactions of the counter electrode with the solution according to the result of the comparison. The reference potential measuring unit includes a reference electrode, a common electrode disposed to be spaced apart from the reference electrode, and at least one nano structure contacting the reference electrode and the common electrode, and having electrical conductivity changing according to the potential of the solution.

Abstract: An integrated circuit (IC) die includes a high capacitance solid state circuit region configured to perform predetermined operations and an RFID block configured for wireless communication with an external source. The RFID block is configured to record results from a plurality of stages of a manufacturing process. The RFID block is further configured to generate an internal BIST command in response to an external command wirelessly received by the RFID. The integrated circuit die also includes a built-in self-test (BIST) block coupled to carry out testing of the high capacitance solid state circuit region in response to the internal BIST command. The RFID block is configured to be capable of storing store information relating to the testing. The RFID block is further configured to enable wireless retrieval of the test results from the testing of the high capacitance solid state circuit region.

Abstract: A semiconductor memory device includes a first cell array including a plurality of unit cells and a bit line sense amplifying unit for sensing and amplifying data signals stored in the unit cells. Each unit cell is provided with a PMOS transistor and a capacitor. Therefore, the semiconductor memory device efficiently operates with low voltage without any degradation of operation speed.

Abstract: The present invention relates to a transistor of a volatile memory device with gate dielectric structure capable of trapping charges and a method for fabricating the same. The transistor in a cell region of a volatile memory device includes a substrate of a first conductive type; a gate dielectric structure capable of trapping charges and formed on the substrate; a gate formed on the gate dielectric structure; a gate insulation layer formed on the gate; a source/drain of a second conductive type formed in a predetermined region of the substrate disposed beneath each lateral side of the gate; and a channel ion implantation region of the first conductive type formed in a predetermined region of the substrate disposed beneath the gate.

Abstract: A nonvolatile ferroelectric memory device includes a plurality of unit cell arrays, wherein each of the plurality of unit cell arrays includes: a bottom word line; a plurality of insulating layers formed on the bottom word line, respectively; a floating channel layer comprising a plurality of channel regions located on the plurality of insulating layers and a plurality of drain and source regions which are alternately electrically connected in series to the plurality of channel regions; a plurality of ferroelectric layers formed respectively on the plurality of channel regions of the floating channel layer; and a plurality of word lines formed on the plurality of ferroelectric layers, respectively. The unit cell array reads and writes a plurality of data by inducing different channel resistance to the plurality of channel regions depending on polarity states of the plurality of ferroelectric layers.

Abstract: The present invention relates to a transistor of a volatile memory device with gate dielectric structure capable of trapping charges and a method for fabricating the same. The transistor in a cell region of a volatile memory device includes a substrate of a first conductive type; a gate dielectric structure capable of trapping charges and formed on the substrate; a gate formed on the gate dielectric structure; a gate insulation layer formed on the gate; a source/drain of a second conductive type formed in a predetermined region of the substrate disposed beneath each lateral side of the gate; and a channel ion implantation region of the first conductive type formed in a predetermined region of the substrate disposed beneath the gate.

Abstract: A method for driving a semiconductor memory device, includes initializing first data corresponding to a refresh time of each corresponding row included in a cell array; storing second data corresponding to column data included in the first row after entering a self refresh mode; setting the first data corresponding to the first row by detecting the refresh time of the first row while performing refresh operations on the other rows in the cell array according to a refresh period selected based on the corresponding first data for predetermined refresh cycles, wherein the refresh operation is not performed on the first row during the predetermined refresh cycles; restoring the second data to the first row; and repeating the above steps for the other rows to thereby set the corresponding first data until the setting step is completed for all rows or the self refresh mode expires.

Abstract: A method for driving a semiconductor memory device, includes initializing first data corresponding to a refresh time of each corresponding row included in a cell array; storing second data corresponding to column data included in the first row after entering a self refresh mode; setting the first data corresponding to the first row by detecting the refresh time of the first row while performing refresh operations on the other rows in the cell array according to a refresh period selected based on the corresponding first data for predetermined refresh cycles, wherein the refresh operation is not performed on the first row during the predetermined refresh cycles; restoring the second data to the first row; and repeating the above steps for the other rows to thereby set the corresponding first data until the setting step is completed for all rows or the self refresh mode expires.

Abstract: An integrated circuit (IC) die includes a high capacitance solid state circuit region configured to perform predetermined operations and an RFID block configured for wireless communication with an external source. The RFID block is configured to record results from a plurality of stages of a manufacturing process. The RFID block is further configured to generate an internal BIST command in response to an external command wirelessly received by the RFID. The integrated circuit die also includes a built-in self-test (BIST) block coupled to carry out testing of the high capacitance solid state circuit region in response to the internal BIST command. The RFID block is configured to be capable of storing store information relating to the testing. The RFID block is further configured to enable wireless retrieval of the test results from the testing of the high capacitance solid state circuit region.

Abstract: A unit memory cell for use in a pseudo static random access memory (SRAM) includes a cell capacitor; a normal accessing transistor whose gate, drain and source are respectively connected to a normal accessing word line, a normal accessing bit line and a storage node of the cell capacitor; and a refresh accessing transistor whose gate, drain and source are respectively connected to a refresh accessing word line, a refresh accessing bit line and the storage node of the cell capacitor.

Abstract: An integrated circuit (IC) die includes a high capacitance solid state circuit region configured to perform predetermined operations and an RFID block configured for wireless communication with an external source. The RFID block is configured to record results from a plurality of stages of a manufacturing process. The RFID block is further configured to generate an internal BIST command in response to an external command wirelessly received by the RFID. The integrated circuit die also includes a built-in self-test (BIST) block coupled to carry out testing of the high capacitance solid state circuit region in response to the internal BIST command. The RFID block is configured to be capable of storing store information relating to the testing. The RFID block is further configured to enable wireless retrieval of the test results from the testing of the high capacitance solid state circuit region.

Abstract: A semiconductor memory device includes a row decoding block for decoding an inputted address to thereby generate a logical unit cell block address and a decoded word line address; a tag block for converting the logical unit cell block address into a physical unit cell block address; a decoded address latching block for latching the decoded word line address to thereby output the decoded word line address as a word line activation signal in response to the physical unit cell block; and a cell area for outputting a data, which is stored therein, in response to the word line activation signal.

Abstract: A RFID device has a nonvolatile ferroelectric memory including a memory cell array area supplied only with a high voltage and a peripheral area supplied with a low voltage, thereby reducing power consumption. The RFID device includes an antenna adapted and configured to transceive a radio frequency signal from an external communication apparatus, an analog block adapted and configured to generate a power voltage in response to the radio frequency signal received from the antenna, a digital block adapted and configured to receive the power voltage from the analog block, transmit a response signal to the analog block and output a memory control signal, and a memory adapted and configured to generate a high voltage with the power voltage and access data in response to the memory control signal.

Abstract: An integrated circuit (IC) includes a high capacitance solid state circuit region configured to perform predetermined operations, a RFID block comprising a FeRAM block for storing data, and an interface unit configured to transfer to the RFID block an externally-provided unique ID for wirelessly identifying the IC, the unique ID being stored in the FeRAM block. The IC further includes a conductive trace extending through predetermined regions of the IC, the conductive trace being configured as an antenna for the RFID block, wherein the RFID block is configured to receive and transmit information to an external source via the antenna.

Abstract: A semiconductor memory device includes a row decoding block for decoding an inputted address to thereby generate a logical unit cell block address and a decoded word line address; a tag block for converting the logical unit cell block address into a physical unit cell block address; a decoded address latching block for latching the decoded word line address to thereby output the decoded word line address as a word line activation signal in response to the physical unit cell block; and a cell area for outputting a data, which is stored therein, in response to the word line activation signal.

Abstract: A nonvolatile ferroelectric memory device includes a plurality of unit cell arrays, wherein each of the plurality of unit cell arrays includes: a bottom word line; a plurality of insulating layers formed on the bottom word line, respectively; a floating channel layer comprising a plurality of channel regions located on the plurality of insulating layers and a plurality of drain and source regions which are alternately electrically connected in series to the plurality of channel regions; a plurality of ferroelectric layers formed respectively on the plurality of channel regions of the floating channel layer; and a plurality of word lines formed on the plurality of ferroelectric layers, respectively. The unit cell array reads and writes a plurality of data by inducing different channel resistance to the plurality of channel regions depending on polarity states of the plurality of ferroelectric layers.

Abstract: A radio frequency identification (RFID) device includes an antenna configured to transmit or receive a radio frequency signal to or from an external communication apparatus; an analog block configured to generate a first power voltage in response to the radio frequency signal; a digital block configured to receive the first power voltage from the analog block, to transmit a response signal to the analog block, and to output a memory control signal; and a memory configured to read/write data in response to the memory control signal, the memory including a high voltage generating unit for generating a second power voltage from the first power voltage, a first portion driven by the second power voltage, and a second portion driven by the first power voltage, wherein the level of the first power voltage is lower than that of the second power voltage.

Abstract: A method for driving a semiconductor memory device, includes initializing first data corresponding to a refresh time of each corresponding row included in a cell array; storing second data corresponding to column data included in the first row after entering a self refresh mode; setting the first data corresponding to the first row by detecting the refresh time of the first row while performing refresh operations on the other rows in the cell array according to a refresh period selected based on the corresponding first data for predetermined refresh cycles, wherein the refresh operation is not performed on the first row during the predetermined refresh cycles; restoring the second data to the first row; and repeating the above steps for the other rows to thereby set the corresponding first data until the setting step is completed for all rows or the self refresh mode expires.

Abstract: A method for driving a semiconductor memory device, includes initializing first data corresponding to a refresh time of each corresponding row included in a cell array; storing second data corresponding to column data included in the first row after entering a self refresh mode; setting the first data corresponding to the first row by detecting the refresh time of the first row while performing refresh operations on the other rows in the cell array according to a refresh period selected based on the corresponding first data for predetermined refresh cycles, wherein the refresh operation is not performed on the first row during the predetermined refresh cycles; restoring the second data to the first row; and repeating the above steps for the other rows to thereby set the corresponding first data until the setting step is completed for all rows or the self refresh mode expires.

Abstract: A memory device includes at least two cell blocks connected to a global bit line for outputting data in response to an instruction; at least one global bit line connection unit for selectively connecting the global bit line to each cell block under control of a control block, one global bit line connection unit being allocated between the two cell blocks; and said control block for controlling output of data stored in each cell block to the global bit line and restoration of the outputted data of the global bit line to the original cell block or another cell block which is determined by depending upon whether data in response to a next instruction is outputted from the original cell block or another cell block.